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Support for Arm VFP v3 registers read/write

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This patch adds support in openOCD to read/write Arm vector/floating 
point registers. This is compatible with Arm vfp v3 target xml in GDB. 
Please refer to binutils-gdb/gdb/features/arm/arm-vfpv3.xml

Change-Id: Id4dd1bddef51c558f1a86300c1a876d159463f18
Signed-off-by: Omair Javaid <omair.javaid@linaro.org>
Reviewed-on: http://openocd.zylin.com/4421
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Tested-by: jenkins
This commit is contained in:
Omair Javaid
2018-02-16 03:08:51 +05:00
committed by Matthias Welwarsky
parent 2830008be0
commit f18ca510b3
5 changed files with 269 additions and 13 deletions
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24
src/target/arm_opcodes.h
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@@ -132,6 +132,30 @@
*/
#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
/* Copies two words from two ARM core registers
* into a doubleword extension register, or
* from a doubleword extension register to two ARM core registers.
* See Armv7-A arch reference manual section A8.8.345
* Rt: Arm core register 1
* Rt2: Arm core register 2
* Vm: The doubleword extension register
* M: m = UInt(M:Vm);
* op: to_arm_registers = (op == ‘1’);
*/
#define ARMV4_5_VMOV(op, Rt2, Rt, M, Vm) \
(0xec400b10 | ((op) << 20) | ((Rt2) << 16) | \
((Rt) << 12) | ((M) << 5) | (Vm))
/* Moves the value of the FPSCR to an ARM core register
* Rt: Arm core register
*/
#define ARMV4_5_VMRS(Rt) (0xeef10a10 | ((Rt) << 12))
/* Moves the value of an ARM core register to the FPSCR.
* Rt: Arm core register
*/
#define ARMV4_5_VMSR(Rt) (0xeee10a10 | ((Rt) << 12))
/* Store data from coprocessor to consecutive memory
* See Armv7-A arch doc section A8.6.187
* P: 1=index mode (offset from Rn)