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cortex_m: read and display core security state

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Change-Id: I0fce3c66af7e98df2dc2258daf0d6af661e29ae7
Signed-off-by: Laurent LEMELE <laurent.lemele@st.com>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5798
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Tarek BOCHKATI
2020-08-11 14:06:04 +01:00
committed by Antonio Borneo
parent 6e33947899
commit f2c83fade3
3 changed files with 25 additions and 1 deletions
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4
src/target/cortex_m.h
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@@ -50,6 +50,7 @@
#define DCB_DCRSR 0xE000EDF4
#define DCB_DCRDR 0xE000EDF8
#define DCB_DEMCR 0xE000EDFC
#define DCB_DSCSR 0xE000EE08
#define DCRSR_WnR BIT(16)
@@ -114,6 +115,9 @@
#define VC_MMERR BIT(4)
#define VC_CORERESET BIT(0)
/* DCB_DSCSR bit and field definitions */
#define DSCSR_CDS BIT(16)
/* NVIC registers */
#define NVIC_ICTR 0xE000E004
#define NVIC_ISE0 0xE000E100