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tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change

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Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

In the TCL scripts distributed with OpenOCD there are 1700+ lines
that should be modified before switching to jimtcl 0.81.

Apply the script below on every script in tcl folder. It fixes
more than 92% of the lines

%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
 #!/usr/bin/perl -Wpi

 my $re_sym = qr{[a-z_][a-z0-9_]*}i;
 my $re_var = qr{(?:\$|\$::)$re_sym};
 my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i;
 my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)};
 my $re_op = qr{<<|>>|[+\-*/&|]};
 my $re_expr = qr{(
     (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item)
     \s*$re_op\s*
     (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\))
 )}x;

 # [expr [dict get $regsC100 SYM] + HEXNUM]
 s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/;

 # [ expr (EXPR) ]
 # [ expr EXPR ]
 # note: $re_expr captures '$3'
 s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/;
 s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/;
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---

Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6159
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo
2021-04-10 01:23:57 +02:00
parent 82b6a41117
commit f5657aa76e
61 changed files with 1592 additions and 1592 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
tcl/chip/atmel/at91/aic.tcl
View File

@@ -1,38 +1,38 @@
set AIC_SMR [expr $AT91C_BASE_AIC + 0x00000000 ]
set AIC_SMR [expr {$AT91C_BASE_AIC + 0x00000000} ]
global AIC_SMR
set AIC_SVR [expr $AT91C_BASE_AIC + 0x00000080 ]
set AIC_SVR [expr {$AT91C_BASE_AIC + 0x00000080} ]
global AIC_SVR
set AIC_IVR [expr $AT91C_BASE_AIC + 0x00000100 ]
set AIC_IVR [expr {$AT91C_BASE_AIC + 0x00000100} ]
global AIC_IVR
set AIC_FVR [expr $AT91C_BASE_AIC + 0x00000104 ]
set AIC_FVR [expr {$AT91C_BASE_AIC + 0x00000104} ]
global AIC_FVR
set AIC_ISR [expr $AT91C_BASE_AIC + 0x00000108 ]
set AIC_ISR [expr {$AT91C_BASE_AIC + 0x00000108} ]
global AIC_ISR
set AIC_IPR [expr $AT91C_BASE_AIC + 0x0000010C ]
set AIC_IPR [expr {$AT91C_BASE_AIC + 0x0000010C} ]
global AIC_IPR
set AIC_IMR [expr $AT91C_BASE_AIC + 0x00000110 ]
set AIC_IMR [expr {$AT91C_BASE_AIC + 0x00000110} ]
global AIC_IMR
set AIC_CISR [expr $AT91C_BASE_AIC + 0x00000114 ]
set AIC_CISR [expr {$AT91C_BASE_AIC + 0x00000114} ]
global AIC_CISR
set AIC_IECR [expr $AT91C_BASE_AIC + 0x00000120 ]
set AIC_IECR [expr {$AT91C_BASE_AIC + 0x00000120} ]
global AIC_IECR
set AIC_IDCR [expr $AT91C_BASE_AIC + 0x00000124 ]
set AIC_IDCR [expr {$AT91C_BASE_AIC + 0x00000124} ]
global AIC_IDCR
set AIC_ICCR [expr $AT91C_BASE_AIC + 0x00000128 ]
set AIC_ICCR [expr {$AT91C_BASE_AIC + 0x00000128} ]
global AIC_ICCR
set AIC_ISCR [expr $AT91C_BASE_AIC + 0x0000012C ]
set AIC_ISCR [expr {$AT91C_BASE_AIC + 0x0000012C} ]
global AIC_ISCR
set AIC_EOICR [expr $AT91C_BASE_AIC + 0x00000130 ]
set AIC_EOICR [expr {$AT91C_BASE_AIC + 0x00000130} ]
global AIC_EOICR
set AIC_SPU [expr $AT91C_BASE_AIC + 0x00000134 ]
set AIC_SPU [expr {$AT91C_BASE_AIC + 0x00000134} ]
global AIC_SPU
set AIC_DCR [expr $AT91C_BASE_AIC + 0x00000138 ]
set AIC_DCR [expr {$AT91C_BASE_AIC + 0x00000138} ]
global AIC_DCR
set AIC_FFER [expr $AT91C_BASE_AIC + 0x00000140 ]
set AIC_FFER [expr {$AT91C_BASE_AIC + 0x00000140} ]
global AIC_FFER
set AIC_FFDR [expr $AT91C_BASE_AIC + 0x00000144 ]
set AIC_FFDR [expr {$AT91C_BASE_AIC + 0x00000144} ]
global AIC_FFDR
set AIC_FFSR [expr $AT91C_BASE_AIC + 0x00000148 ]
set AIC_FFSR [expr {$AT91C_BASE_AIC + 0x00000148} ]
global AIC_FFSR
@@ -54,7 +54,7 @@ proc show_AIC_IMR_helper { NAME ADDR VAL } {
proc show_AIC { } {
global AIC_SMR
if [catch { mem2array aaa 32 $AIC_SMR [expr 32 * 4] } msg ] {
if [catch { mem2array aaa 32 $AIC_SMR [expr {32 * 4}] } msg ] {
error [format "%s (%s)" $msg AIC_SMR]
}
echo "AIC_SMR: Mode & Type"
@@ -71,7 +71,7 @@ proc show_AIC { } {
incr x
}
global AIC_SVR
if [catch { mem2array aaa 32 $AIC_SVR [expr 32 * 4] } msg ] {
if [catch { mem2array aaa 32 $AIC_SVR [expr {32 * 4}] } msg ] {
error [format "%s (%s)" $msg AIC_SVR]
}
echo "AIC_SVR: Vectors"

198
tcl/chip/atmel/at91/at91_pmc.cfg
View File

@@ -1,113 +1,113 @@
set AT91_PMC_SCER [expr ($AT91_PMC + 0x00)] ;# System Clock Enable Register
set AT91_PMC_SCDR [expr ($AT91_PMC + 0x04)] ;# System Clock Disable Register
set AT91_PMC_SCER [expr {$AT91_PMC + 0x00}] ;# System Clock Enable Register
set AT91_PMC_SCDR [expr {$AT91_PMC + 0x04}] ;# System Clock Disable Register
set AT91_PMC_SCSR [expr ($AT91_PMC + 0x08)] ;# System Clock Status Register
set AT91_PMC_PCK [expr (1 << 0)] ;# Processor Clock
set AT91RM9200_PMC_UDP [expr (1 << 1)] ;# USB Devcice Port Clock [AT91RM9200 only]
set AT91RM9200_PMC_MCKUDP [expr (1 << 2)] ;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only]
set AT91CAP9_PMC_DDR [expr (1 << 2)] ;# DDR Clock [CAP9 revC & some SAM9 only]
set AT91RM9200_PMC_UHP [expr (1 << 4)] ;# USB Host Port Clock [AT91RM9200 only]
set AT91SAM926x_PMC_UHP [expr (1 << 6)] ;# USB Host Port Clock [AT91SAM926x only]
set AT91CAP9_PMC_UHP [expr (1 << 6)] ;# USB Host Port Clock [AT91CAP9 only]
set AT91SAM926x_PMC_UDP [expr (1 << 7)] ;# USB Devcice Port Clock [AT91SAM926x only]
set AT91_PMC_PCK0 [expr (1 << 8)] ;# Programmable Clock 0
set AT91_PMC_PCK1 [expr (1 << 9)] ;# Programmable Clock 1
set AT91_PMC_PCK2 [expr (1 << 10)] ;# Programmable Clock 2
set AT91_PMC_PCK3 [expr (1 << 11)] ;# Programmable Clock 3
set AT91_PMC_HCK0 [expr (1 << 16)] ;# AHB Clock (USB host) [AT91SAM9261 only]
set AT91_PMC_HCK1 [expr (1 << 17)] ;# AHB Clock (LCD) [AT91SAM9261 only]
set AT91_PMC_SCSR [expr {$AT91_PMC + 0x08}] ;# System Clock Status Register
set AT91_PMC_PCK [expr {1 << 0}] ;# Processor Clock
set AT91RM9200_PMC_UDP [expr {1 << 1}] ;# USB Devcice Port Clock [AT91RM9200 only]
set AT91RM9200_PMC_MCKUDP [expr {1 << 2}] ;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only]
set AT91CAP9_PMC_DDR [expr {1 << 2}] ;# DDR Clock [CAP9 revC & some SAM9 only]
set AT91RM9200_PMC_UHP [expr {1 << 4}] ;# USB Host Port Clock [AT91RM9200 only]
set AT91SAM926x_PMC_UHP [expr {1 << 6}] ;# USB Host Port Clock [AT91SAM926x only]
set AT91CAP9_PMC_UHP [expr {1 << 6}] ;# USB Host Port Clock [AT91CAP9 only]
set AT91SAM926x_PMC_UDP [expr {1 << 7}] ;# USB Devcice Port Clock [AT91SAM926x only]
set AT91_PMC_PCK0 [expr {1 << 8}] ;# Programmable Clock 0
set AT91_PMC_PCK1 [expr {1 << 9}] ;# Programmable Clock 1
set AT91_PMC_PCK2 [expr {1 << 10}] ;# Programmable Clock 2
set AT91_PMC_PCK3 [expr {1 << 11}] ;# Programmable Clock 3
set AT91_PMC_HCK0 [expr {1 << 16}] ;# AHB Clock (USB host) [AT91SAM9261 only]
set AT91_PMC_HCK1 [expr {1 << 17}] ;# AHB Clock (LCD) [AT91SAM9261 only]
set AT91_PMC_PCER [expr ($AT91_PMC + 0x10)] ;# Peripheral Clock Enable Register
set AT91_PMC_PCDR [expr ($AT91_PMC + 0x14)] ;# Peripheral Clock Disable Register
set AT91_PMC_PCSR [expr ($AT91_PMC + 0x18)] ;# Peripheral Clock Status Register
set AT91_PMC_PCER [expr {$AT91_PMC + 0x10}] ;# Peripheral Clock Enable Register
set AT91_PMC_PCDR [expr {$AT91_PMC + 0x14}] ;# Peripheral Clock Disable Register
set AT91_PMC_PCSR [expr {$AT91_PMC + 0x18}] ;# Peripheral Clock Status Register
set AT91_CKGR_UCKR [expr ($AT91_PMC + 0x1C)] ;# UTMI Clock Register [some SAM9, CAP9]
set AT91_PMC_UPLLEN [expr (1 << 16)] ;# UTMI PLL Enable
set AT91_PMC_UPLLCOUNT [expr (0xf << 20)] ;# UTMI PLL Start-up Time
set AT91_PMC_BIASEN [expr (1 << 24)] ;# UTMI BIAS Enable
set AT91_PMC_BIASCOUNT [expr (0xf << 28)] ;# UTMI BIAS Start-up Time
set AT91_CKGR_UCKR [expr {$AT91_PMC + 0x1C}] ;# UTMI Clock Register [some SAM9, CAP9]
set AT91_PMC_UPLLEN [expr {1 << 16}] ;# UTMI PLL Enable
set AT91_PMC_UPLLCOUNT [expr {0xf << 20}] ;# UTMI PLL Start-up Time
set AT91_PMC_BIASEN [expr {1 << 24}] ;# UTMI BIAS Enable
set AT91_PMC_BIASCOUNT [expr {0xf << 28}] ;# UTMI BIAS Start-up Time
set AT91_CKGR_MOR [expr ($AT91_PMC + 0x20)] ;# Main Oscillator Register [not on SAM9RL]
set AT91_PMC_MOSCEN [expr (1 << 0)] ;# Main Oscillator Enable
set AT91_PMC_OSCBYPASS [expr (1 << 1)] ;# Oscillator Bypass [SAM9x, CAP9]
set AT91_PMC_OSCOUNT [expr (0xff << 8)] ;# Main Oscillator Start-up Time
set AT91_CKGR_MOR [expr {$AT91_PMC + 0x20}] ;# Main Oscillator Register [not on SAM9RL]
set AT91_PMC_MOSCEN [expr {1 << 0}] ;# Main Oscillator Enable
set AT91_PMC_OSCBYPASS [expr {1 << 1}] ;# Oscillator Bypass [SAM9x, CAP9]
set AT91_PMC_OSCOUNT [expr {0xff << 8}] ;# Main Oscillator Start-up Time
set AT91_CKGR_MCFR [expr ($AT91_PMC + 0x24)] ;# Main Clock Frequency Register
set AT91_PMC_MAINF [expr (0xffff << 0)] ;# Main Clock Frequency
set AT91_PMC_MAINRDY [expr (1 << 16)] ;# Main Clock Ready
set AT91_CKGR_MCFR [expr {$AT91_PMC + 0x24}] ;# Main Clock Frequency Register
set AT91_PMC_MAINF [expr {0xffff << 0}] ;# Main Clock Frequency
set AT91_PMC_MAINRDY [expr {1 << 16}] ;# Main Clock Ready
set AT91_CKGR_PLLAR [expr ($AT91_PMC + 0x28)] ;# PLL A Register
set AT91_CKGR_PLLBR [expr ($AT91_PMC + 0x2c)] ;# PLL B Register
set AT91_PMC_DIV [expr (0xff << 0)] ;# Divider
set AT91_PMC_PLLCOUNT [expr (0x3f << 8)] ;# PLL Counter
set AT91_PMC_OUT [expr (3 << 14)] ;# PLL Clock Frequency Range
set AT91_PMC_MUL [expr (0x7ff << 16)] ;# PLL Multiplier
set AT91_PMC_USBDIV [expr (3 << 28)] ;# USB Divisor (PLLB only)
set AT91_PMC_USBDIV_1 [expr (0 << 28)]
set AT91_PMC_USBDIV_2 [expr (1 << 28)]
set AT91_PMC_USBDIV_4 [expr (2 << 28)]
set AT91_PMC_USB96M [expr (1 << 28)] ;# Divider by 2 Enable (PLLB only)
set AT91_PMC_PLLA_WR_ERRATA [expr (1 << 29)] ;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register
set AT91_CKGR_PLLAR [expr {$AT91_PMC + 0x28}] ;# PLL A Register
set AT91_CKGR_PLLBR [expr {$AT91_PMC + 0x2c}] ;# PLL B Register
set AT91_PMC_DIV [expr {0xff << 0}] ;# Divider
set AT91_PMC_PLLCOUNT [expr {0x3f << 8}] ;# PLL Counter
set AT91_PMC_OUT [expr {3 << 14}] ;# PLL Clock Frequency Range
set AT91_PMC_MUL [expr {0x7ff << 16}] ;# PLL Multiplier
set AT91_PMC_USBDIV [expr {3 << 28}] ;# USB Divisor (PLLB only)
set AT91_PMC_USBDIV_1 [expr {0 << 28}]
set AT91_PMC_USBDIV_2 [expr {1 << 28}]
set AT91_PMC_USBDIV_4 [expr {2 << 28}]
set AT91_PMC_USB96M [expr {1 << 28}] ;# Divider by 2 Enable (PLLB only)
set AT91_PMC_PLLA_WR_ERRATA [expr {1 << 29}] ;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register
set AT91_PMC_MCKR [expr ($AT91_PMC + 0x30)] ;# Master Clock Register
set AT91_PMC_CSS [expr (3 << 0)] ;# Master Clock Selection
set AT91_PMC_CSS_SLOW [expr (0 << 0)]
set AT91_PMC_CSS_MAIN [expr (1 << 0)]
set AT91_PMC_CSS_PLLA [expr (2 << 0)]
set AT91_PMC_CSS_PLLB [expr (3 << 0)]
set AT91_PMC_CSS_UPLL [expr (3 << 0)] ;# [some SAM9 only]
set AT91_PMC_PRES [expr (7 << 2)] ;# Master Clock Prescaler
set AT91_PMC_PRES_1 [expr (0 << 2)]
set AT91_PMC_PRES_2 [expr (1 << 2)]
set AT91_PMC_PRES_4 [expr (2 << 2)]
set AT91_PMC_PRES_8 [expr (3 << 2)]
set AT91_PMC_PRES_16 [expr (4 << 2)]
set AT91_PMC_PRES_32 [expr (5 << 2)]
set AT91_PMC_PRES_64 [expr (6 << 2)]
set AT91_PMC_MDIV [expr (3 << 8)] ;# Master Clock Division
set AT91RM9200_PMC_MDIV_1 [expr (0 << 8)] ;# [AT91RM9200 only]
set AT91RM9200_PMC_MDIV_2 [expr (1 << 8)]
set AT91RM9200_PMC_MDIV_3 [expr (2 << 8)]
set AT91RM9200_PMC_MDIV_4 [expr (3 << 8)]
set AT91SAM9_PMC_MDIV_1 [expr (0 << 8)] ;# [SAM9,CAP9 only]
set AT91SAM9_PMC_MDIV_2 [expr (1 << 8)]
set AT91SAM9_PMC_MDIV_4 [expr (2 << 8)]
set AT91SAM9_PMC_MDIV_6 [expr (3 << 8)] ;# [some SAM9 only]
set AT91SAM9_PMC_MDIV_3 [expr (3 << 8)] ;# [some SAM9 only]
set AT91_PMC_PDIV [expr (1 << 12)] ;# Processor Clock Division [some SAM9 only]
set AT91_PMC_PDIV_1 [expr (0 << 12)]
set AT91_PMC_PDIV_2 [expr (1 << 12)]
set AT91_PMC_PLLADIV2 [expr (1 << 12)] ;# PLLA divisor by 2 [some SAM9 only]
set AT91_PMC_PLLADIV2_OFF [expr (0 << 12)]
set AT91_PMC_PLLADIV2_ON [expr (1 << 12)]
set AT91_PMC_MCKR [expr {$AT91_PMC + 0x30}] ;# Master Clock Register
set AT91_PMC_CSS [expr {3 << 0}] ;# Master Clock Selection
set AT91_PMC_CSS_SLOW [expr {0 << 0}]
set AT91_PMC_CSS_MAIN [expr {1 << 0}]
set AT91_PMC_CSS_PLLA [expr {2 << 0}]
set AT91_PMC_CSS_PLLB [expr {3 << 0}]
set AT91_PMC_CSS_UPLL [expr {3 << 0}] ;# [some SAM9 only]
set AT91_PMC_PRES [expr {7 << 2}] ;# Master Clock Prescaler
set AT91_PMC_PRES_1 [expr {0 << 2}]
set AT91_PMC_PRES_2 [expr {1 << 2}]
set AT91_PMC_PRES_4 [expr {2 << 2}]
set AT91_PMC_PRES_8 [expr {3 << 2}]
set AT91_PMC_PRES_16 [expr {4 << 2}]
set AT91_PMC_PRES_32 [expr {5 << 2}]
set AT91_PMC_PRES_64 [expr {6 << 2}]
set AT91_PMC_MDIV [expr {3 << 8}] ;# Master Clock Division
set AT91RM9200_PMC_MDIV_1 [expr {0 << 8}] ;# [AT91RM9200 only]
set AT91RM9200_PMC_MDIV_2 [expr {1 << 8}]
set AT91RM9200_PMC_MDIV_3 [expr {2 << 8}]
set AT91RM9200_PMC_MDIV_4 [expr {3 << 8}]
set AT91SAM9_PMC_MDIV_1 [expr {0 << 8}] ;# [SAM9,CAP9 only]
set AT91SAM9_PMC_MDIV_2 [expr {1 << 8}]
set AT91SAM9_PMC_MDIV_4 [expr {2 << 8}]
set AT91SAM9_PMC_MDIV_6 [expr {3 << 8}] ;# [some SAM9 only]
set AT91SAM9_PMC_MDIV_3 [expr {3 << 8}] ;# [some SAM9 only]
set AT91_PMC_PDIV [expr {1 << 12}] ;# Processor Clock Division [some SAM9 only]
set AT91_PMC_PDIV_1 [expr {0 << 12}]
set AT91_PMC_PDIV_2 [expr {1 << 12}]
set AT91_PMC_PLLADIV2 [expr {1 << 12}] ;# PLLA divisor by 2 [some SAM9 only]
set AT91_PMC_PLLADIV2_OFF [expr {0 << 12}]
set AT91_PMC_PLLADIV2_ON [expr {1 << 12}]
set AT91_PMC_USB [expr ($AT91_PMC + 0x38)] ;# USB Clock Register [some SAM9 only]
set AT91_PMC_USBS [expr (0x1 << 0)] ;# USB OHCI Input clock selection
set AT91_PMC_USBS_PLLA [expr (0 << 0)]
set AT91_PMC_USBS_UPLL [expr (1 << 0)]
set AT91_PMC_OHCIUSBDIV [expr (0xF << 8)] ;# Divider for USB OHCI Clock
set AT91_PMC_USB [expr {$AT91_PMC + 0x38}] ;# USB Clock Register [some SAM9 only]
set AT91_PMC_USBS [expr {0x1 << 0}] ;# USB OHCI Input clock selection
set AT91_PMC_USBS_PLLA [expr {0 << 0}]
set AT91_PMC_USBS_UPLL [expr {1 << 0}]
set AT91_PMC_OHCIUSBDIV [expr {0xF << 8}] ;# Divider for USB OHCI Clock
;# set AT91_PMC_PCKR(n) [expr ($AT91_PMC + 0x40 + ((n) * 4))] ;# Programmable Clock 0-N Registers
set AT91_PMC_CSSMCK [expr (0x1 << 8)] ;# CSS or Master Clock Selection
set AT91_PMC_CSSMCK_CSS [expr (0 << 8)]
set AT91_PMC_CSSMCK_MCK [expr (1 << 8)]
set AT91_PMC_CSSMCK [expr {0x1 << 8}] ;# CSS or Master Clock Selection
set AT91_PMC_CSSMCK_CSS [expr {0 << 8}]
set AT91_PMC_CSSMCK_MCK [expr {1 << 8}]
set AT91_PMC_IER [expr ($AT91_PMC + 0x60)] ;# Interrupt Enable Register
set AT91_PMC_IDR [expr ($AT91_PMC + 0x64)] ;# Interrupt Disable Register
set AT91_PMC_SR [expr ($AT91_PMC + 0x68)] ;# Status Register
set AT91_PMC_MOSCS [expr (1 << 0)] ;# MOSCS Flag
set AT91_PMC_LOCKA [expr (1 << 1)] ;# PLLA Lock
set AT91_PMC_LOCKB [expr (1 << 2)] ;# PLLB Lock
set AT91_PMC_MCKRDY [expr (1 << 3)] ;# Master Clock
set AT91_PMC_LOCKU [expr (1 << 6)] ;# UPLL Lock [some SAM9, AT91CAP9 only]
set AT91_PMC_OSCSEL [expr (1 << 7)] ;# Slow Clock Oscillator [AT91CAP9 revC only]
set AT91_PMC_PCK0RDY [expr (1 << 8)] ;# Programmable Clock 0
set AT91_PMC_PCK1RDY [expr (1 << 9)] ;# Programmable Clock 1
set AT91_PMC_PCK2RDY [expr (1 << 10)] ;# Programmable Clock 2
set AT91_PMC_PCK3RDY [expr (1 << 11)] ;# Programmable Clock 3
set AT91_PMC_IMR [expr ($AT91_PMC + 0x6c)] ;# Interrupt Mask Register
set AT91_PMC_IER [expr {$AT91_PMC + 0x60}] ;# Interrupt Enable Register
set AT91_PMC_IDR [expr {$AT91_PMC + 0x64}] ;# Interrupt Disable Register
set AT91_PMC_SR [expr {$AT91_PMC + 0x68}] ;# Status Register
set AT91_PMC_MOSCS [expr {1 << 0}] ;# MOSCS Flag
set AT91_PMC_LOCKA [expr {1 << 1}] ;# PLLA Lock
set AT91_PMC_LOCKB [expr {1 << 2}] ;# PLLB Lock
set AT91_PMC_MCKRDY [expr {1 << 3}] ;# Master Clock
set AT91_PMC_LOCKU [expr {1 << 6}] ;# UPLL Lock [some SAM9, AT91CAP9 only]
set AT91_PMC_OSCSEL [expr {1 << 7}] ;# Slow Clock Oscillator [AT91CAP9 revC only]
set AT91_PMC_PCK0RDY [expr {1 << 8}] ;# Programmable Clock 0
set AT91_PMC_PCK1RDY [expr {1 << 9}] ;# Programmable Clock 1
set AT91_PMC_PCK2RDY [expr {1 << 10}] ;# Programmable Clock 2
set AT91_PMC_PCK3RDY [expr {1 << 11}] ;# Programmable Clock 3
set AT91_PMC_IMR [expr {$AT91_PMC + 0x6c}] ;# Interrupt Mask Register
set AT91_PMC_PROT [expr ($AT91_PMC + 0xe4)] ;# Protect Register [AT91CAP9 revC only]
set AT91_PMC_PROT [expr {$AT91_PMC + 0xe4}] ;# Protect Register [AT91CAP9 revC only]
set AT91_PMC_PROTKEY 0x504d4301 ;# Activation Code
set AT91_PMC_VER [expr ($AT91_PMC + 0xfc)] ;# PMC Module Version [AT91CAP9 only]
set AT91_PMC_VER [expr {$AT91_PMC + 0xfc}] ;# PMC Module Version [AT91CAP9 only]

38
tcl/chip/atmel/at91/at91_rstc.cfg
View File

@@ -1,21 +1,21 @@
set AT91_RSTC_CR [expr ($AT91_RSTC + 0x00)] ;# Reset Controller Control Register
set AT91_RSTC_PROCRST [expr (1 << 0)] ;# Processor Reset
set AT91_RSTC_PERRST [expr (1 << 2)] ;# Peripheral Reset
set AT91_RSTC_EXTRST [expr (1 << 3)] ;# External Reset
set AT91_RSTC_KEY [expr (0xa5 << 24)] ;# KEY Password
set AT91_RSTC_CR [expr {$AT91_RSTC + 0x00}] ;# Reset Controller Control Register
set AT91_RSTC_PROCRST [expr {1 << 0}] ;# Processor Reset
set AT91_RSTC_PERRST [expr {1 << 2}] ;# Peripheral Reset
set AT91_RSTC_EXTRST [expr {1 << 3}] ;# External Reset
set AT91_RSTC_KEY [expr {0xa5 << 24}] ;# KEY Password
set AT91_RSTC_SR [expr ($AT91_RSTC + 0x04)] ;# Reset Controller Status Register
set AT91_RSTC_URSTS [expr (1 << 0)] ;# User Reset Status
set AT91_RSTC_RSTTYP [expr (7 << 8)] ;# Reset Type
set AT91_RSTC_RSTTYP_GENERAL [expr (0 << 8)]
set AT91_RSTC_RSTTYP_WAKEUP [expr (1 << 8)]
set AT91_RSTC_RSTTYP_WATCHDOG [expr (2 << 8)]
set AT91_RSTC_RSTTYP_SOFTWARE [expr (3 << 8)]
set AT91_RSTC_RSTTYP_USER [expr (4 << 8)]
set AT91_RSTC_NRSTL [expr (1 << 16)] ;# NRST Pin Level
set AT91_RSTC_SRCMP [expr (1 << 17)] ;# Software Reset Command in Progress
set AT91_RSTC_SR [expr {$AT91_RSTC + 0x04}] ;# Reset Controller Status Register
set AT91_RSTC_URSTS [expr {1 << 0}] ;# User Reset Status
set AT91_RSTC_RSTTYP [expr {7 << 8}] ;# Reset Type
set AT91_RSTC_RSTTYP_GENERAL [expr {0 << 8}]
set AT91_RSTC_RSTTYP_WAKEUP [expr {1 << 8}]
set AT91_RSTC_RSTTYP_WATCHDOG [expr {2 << 8}]
set AT91_RSTC_RSTTYP_SOFTWARE [expr {3 << 8}]
set AT91_RSTC_RSTTYP_USER [expr {4 << 8}]
set AT91_RSTC_NRSTL [expr {1 << 16}] ;# NRST Pin Level
set AT91_RSTC_SRCMP [expr {1 << 17}] ;# Software Reset Command in Progress
set AT91_RSTC_MR [expr ($AT91_RSTC + 0x08)] ;# Reset Controller Mode Register
set AT91_RSTC_URSTEN [expr (1 << 0)] ;# User Reset Enable
set AT91_RSTC_URSTIEN [expr (1 << 4)] ;# User Reset Interrupt Enable
set AT91_RSTC_ERSTL [expr (0xf << 8)] ;# External Reset Length
set AT91_RSTC_MR [expr {$AT91_RSTC + 0x08}] ;# Reset Controller Mode Register
set AT91_RSTC_URSTEN [expr {1 << 0}] ;# User Reset Enable
set AT91_RSTC_URSTIEN [expr {1 << 4}] ;# User Reset Interrupt Enable
set AT91_RSTC_ERSTL [expr {0xf << 8}] ;# External Reset Length

30
tcl/chip/atmel/at91/at91_wdt.cfg
View File

@@ -1,17 +1,17 @@
set AT91_WDT_CR [expr ($AT91_WDT + 0x00)] ;# Watchdog Control Register
set AT91_WDT_WDRSTT [expr (1 << 0)] ;# Restart
set AT91_WDT_KEY [expr (0xa5 << 24)] ;# KEY Password
set AT91_WDT_CR [expr {$AT91_WDT + 0x00}] ;# Watchdog Control Register
set AT91_WDT_WDRSTT [expr {1 << 0}] ;# Restart
set AT91_WDT_KEY [expr {0xa5 << 24}] ;# KEY Password
set AT91_WDT_MR [expr ($AT91_WDT + 0x04)] ;# Watchdog Mode Register
set AT91_WDT_WDV [expr (0xfff << 0)] ;# Counter Value
set AT91_WDT_WDFIEN [expr (1 << 12)] ;# Fault Interrupt Enable
set AT91_WDT_WDRSTEN [expr (1 << 13)] ;# Reset Processor
set AT91_WDT_WDRPROC [expr (1 << 14)] ;# Timer Restart
set AT91_WDT_WDDIS [expr (1 << 15)] ;# Watchdog Disable
set AT91_WDT_WDD [expr (0xfff << 16)] ;# Delta Value
set AT91_WDT_WDDBGHLT [expr (1 << 28)] ;# Debug Halt
set AT91_WDT_WDIDLEHLT [expr (1 << 29)] ;# Idle Halt
set AT91_WDT_MR [expr {$AT91_WDT + 0x04}] ;# Watchdog Mode Register
set AT91_WDT_WDV [expr {0xfff << 0}] ;# Counter Value
set AT91_WDT_WDFIEN [expr {1 << 12}] ;# Fault Interrupt Enable
set AT91_WDT_WDRSTEN [expr {1 << 13}] ;# Reset Processor
set AT91_WDT_WDRPROC [expr {1 << 14}] ;# Timer Restart
set AT91_WDT_WDDIS [expr {1 << 15}] ;# Watchdog Disable
set AT91_WDT_WDD [expr {0xfff << 16}] ;# Delta Value
set AT91_WDT_WDDBGHLT [expr {1 << 28}] ;# Debug Halt
set AT91_WDT_WDIDLEHLT [expr {1 << 29}] ;# Idle Halt
set AT91_WDT_SR [expr ($AT91_WDT + 0x08)] ;# Watchdog Status Register
set AT91_WDT_WDUNF [expr (1 << 0)] ;# Watchdog Underflow
set AT91_WDT_WDERR [expr (1 << 1)] ;# Watchdog Error
set AT91_WDT_SR [expr {$AT91_WDT + 0x08}] ;# Watchdog Status Register
set AT91_WDT_WDUNF [expr {1 << 0}] ;# Watchdog Underflow
set AT91_WDT_WDERR [expr {1 << 1}] ;# Watchdog Error

82
tcl/chip/atmel/at91/at91sam9261_matrix.cfg
View File

@@ -1,46 +1,46 @@
set AT91_MATRIX_MCFG [expr ($AT91_MATRIX + 0x00)] ;# Master Configuration Register #
set AT91_MATRIX_RCB0 [expr (1 << 0)] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
set AT91_MATRIX_RCB1 [expr (1 << 1)] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
set AT91_MATRIX_MCFG [expr {$AT91_MATRIX + 0x00}] ;# Master Configuration Register #
set AT91_MATRIX_RCB0 [expr {1 << 0}] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
set AT91_MATRIX_RCB1 [expr {1 << 1}] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
set AT91_MATRIX_SCFG0 [expr ($AT91_MATRIX + 0x04)] ;# Slave Configuration Register 0
set AT91_MATRIX_SCFG1 [expr ($AT91_MATRIX + 0x08)] ;# Slave Configuration Register 1
set AT91_MATRIX_SCFG2 [expr ($AT91_MATRIX + 0x0C)] ;# Slave Configuration Register 2
set AT91_MATRIX_SCFG3 [expr ($AT91_MATRIX + 0x10)] ;# Slave Configuration Register 3
set AT91_MATRIX_SCFG4 [expr ($AT91_MATRIX + 0x14)] ;# Slave Configuration Register 4
set AT91_MATRIX_SLOT_CYCLE [expr (0xff << 0)] ;# Maximum Number of Allowed Cycles for a Burst
set AT91_MATRIX_DEFMSTR_TYPE [expr (3 << 16)] ;# Default Master Type
set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr (0 << 16)]
set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr (1 << 16)]
set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr (2 << 16)]
set AT91_MATRIX_FIXED_DEFMSTR [expr (7 << 18)] ;# Fixed Index of Default Master
set AT91_MATRIX_SCFG0 [expr {$AT91_MATRIX + 0x04}] ;# Slave Configuration Register 0
set AT91_MATRIX_SCFG1 [expr {$AT91_MATRIX + 0x08}] ;# Slave Configuration Register 1
set AT91_MATRIX_SCFG2 [expr {$AT91_MATRIX + 0x0C}] ;# Slave Configuration Register 2
set AT91_MATRIX_SCFG3 [expr {$AT91_MATRIX + 0x10}] ;# Slave Configuration Register 3
set AT91_MATRIX_SCFG4 [expr {$AT91_MATRIX + 0x14}] ;# Slave Configuration Register 4
set AT91_MATRIX_SLOT_CYCLE [expr {0xff << 0}] ;# Maximum Number of Allowed Cycles for a Burst
set AT91_MATRIX_DEFMSTR_TYPE [expr {3 << 16}] ;# Default Master Type
set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr {0 << 16}]
set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr {1 << 16}]
set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr {2 << 16}]
set AT91_MATRIX_FIXED_DEFMSTR [expr {7 << 18}] ;# Fixed Index of Default Master
set AT91_MATRIX_TCR [expr ($AT91_MATRIX + 0x24)] ;# TCM Configuration Register
set AT91_MATRIX_ITCM_SIZE [expr (0xf << 0)] ;# Size of ITCM enabled memory block
set AT91_MATRIX_ITCM_0 [expr (0 << 0)]
set AT91_MATRIX_ITCM_16 [expr (5 << 0)]
set AT91_MATRIX_ITCM_32 [expr (6 << 0)]
set AT91_MATRIX_ITCM_64 [expr (7 << 0)]
set AT91_MATRIX_DTCM_SIZE [expr (0xf << 4)] ;# Size of DTCM enabled memory block
set AT91_MATRIX_DTCM_0 [expr (0 << 4)]
set AT91_MATRIX_DTCM_16 [expr (5 << 4)]
set AT91_MATRIX_DTCM_32 [expr (6 << 4)]
set AT91_MATRIX_DTCM_64 [expr (7 << 4)]
set AT91_MATRIX_TCR [expr {$AT91_MATRIX + 0x24}] ;# TCM Configuration Register
set AT91_MATRIX_ITCM_SIZE [expr {0xf << 0}] ;# Size of ITCM enabled memory block
set AT91_MATRIX_ITCM_0 [expr {0 << 0}]
set AT91_MATRIX_ITCM_16 [expr {5 << 0}]
set AT91_MATRIX_ITCM_32 [expr {6 << 0}]
set AT91_MATRIX_ITCM_64 [expr {7 << 0}]
set AT91_MATRIX_DTCM_SIZE [expr {0xf << 4}] ;# Size of DTCM enabled memory block
set AT91_MATRIX_DTCM_0 [expr {0 << 4}]
set AT91_MATRIX_DTCM_16 [expr {5 << 4}]
set AT91_MATRIX_DTCM_32 [expr {6 << 4}]
set AT91_MATRIX_DTCM_64 [expr {7 << 4}]
set AT91_MATRIX_EBICSA [expr ($AT91_MATRIX + 0x30)] ;# EBI Chip Select Assignment Register
set AT91_MATRIX_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment
set AT91_MATRIX_CS1A_SMC [expr (0 << 1)]
set AT91_MATRIX_CS1A_SDRAMC [expr (1 << 1)]
set AT91_MATRIX_CS3A [expr (1 << 3)] ;# Chip Select 3 Assignment
set AT91_MATRIX_CS3A_SMC [expr (0 << 3)]
set AT91_MATRIX_CS3A_SMC_SMARTMEDIA [expr (1 << 3)]
set AT91_MATRIX_CS4A [expr (1 << 4)] ;# Chip Select 4 Assignment
set AT91_MATRIX_CS4A_SMC [expr (0 << 4)]
set AT91_MATRIX_CS4A_SMC_CF1 [expr (1 << 4)]
set AT91_MATRIX_CS5A [expr (1 << 5)] ;# Chip Select 5 Assignment
set AT91_MATRIX_CS5A_SMC [expr (0 << 5)]
set AT91_MATRIX_CS5A_SMC_CF2 [expr (1 << 5)]
set AT91_MATRIX_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration
set AT91_MATRIX_EBICSA [expr {$AT91_MATRIX + 0x30}] ;# EBI Chip Select Assignment Register
set AT91_MATRIX_CS1A [expr {1 << 1}] ;# Chip Select 1 Assignment
set AT91_MATRIX_CS1A_SMC [expr {0 << 1}]
set AT91_MATRIX_CS1A_SDRAMC [expr {1 << 1}]
set AT91_MATRIX_CS3A [expr {1 << 3}] ;# Chip Select 3 Assignment
set AT91_MATRIX_CS3A_SMC [expr {0 << 3}]
set AT91_MATRIX_CS3A_SMC_SMARTMEDIA [expr {1 << 3}]
set AT91_MATRIX_CS4A [expr {1 << 4}] ;# Chip Select 4 Assignment
set AT91_MATRIX_CS4A_SMC [expr {0 << 4}]
set AT91_MATRIX_CS4A_SMC_CF1 [expr {1 << 4}]
set AT91_MATRIX_CS5A [expr {1 << 5}] ;# Chip Select 5 Assignment
set AT91_MATRIX_CS5A_SMC [expr {0 << 5}]
set AT91_MATRIX_CS5A_SMC_CF2 [expr {1 << 5}]
set AT91_MATRIX_DBPUC [expr {1 << 8}] ;# Data Bus Pull-up Configuration
set AT91_MATRIX_USBPUCR [expr ($AT91_MATRIX + 0x34)] ;# USB Pad Pull-Up Control Register
set AT91_MATRIX_USBPUCR_PUON [expr (1 << 30)] ;# USB Device PAD Pull-up Enable
set AT91_MATRIX_USBPUCR [expr {$AT91_MATRIX + 0x34}] ;# USB Pad Pull-Up Control Register
set AT91_MATRIX_USBPUCR_PUON [expr {1 << 30}] ;# USB Device PAD Pull-up Enable

208
tcl/chip/atmel/at91/at91sam9263_matrix.cfg
View File

@@ -1,110 +1,110 @@
set AT91_MATRIX_MCFG0 [expr ($AT91_MATRIX + 0x00)] ;# Master Configuration Register 0
set AT91_MATRIX_MCFG1 [expr ($AT91_MATRIX + 0x04)] ;# Master Configuration Register 1
set AT91_MATRIX_MCFG2 [expr ($AT91_MATRIX + 0x08)] ;# Master Configuration Register 2
set AT91_MATRIX_MCFG3 [expr ($AT91_MATRIX + 0x0C)] ;# Master Configuration Register 3
set AT91_MATRIX_MCFG4 [expr ($AT91_MATRIX + 0x10)] ;# Master Configuration Register 4
set AT91_MATRIX_MCFG5 [expr ($AT91_MATRIX + 0x14)] ;# Master Configuration Register 5
set AT91_MATRIX_MCFG6 [expr ($AT91_MATRIX + 0x18)] ;# Master Configuration Register 6
set AT91_MATRIX_MCFG7 [expr ($AT91_MATRIX + 0x1C)] ;# Master Configuration Register 7
set AT91_MATRIX_MCFG8 [expr ($AT91_MATRIX + 0x20)] ;# Master Configuration Register 8
set AT91_MATRIX_ULBT [expr (7 << 0)] ;# Undefined Length Burst Type
set AT91_MATRIX_ULBT_INFINITE [expr (0 << 0)]
set AT91_MATRIX_ULBT_SINGLE [expr (1 << 0)]
set AT91_MATRIX_ULBT_FOUR [expr (2 << 0)]
set AT91_MATRIX_ULBT_EIGHT [expr (3 << 0)]
set AT91_MATRIX_ULBT_SIXTEEN [expr (4 << 0)]
set AT91_MATRIX_MCFG0 [expr {$AT91_MATRIX + 0x00}] ;# Master Configuration Register 0
set AT91_MATRIX_MCFG1 [expr {$AT91_MATRIX + 0x04}] ;# Master Configuration Register 1
set AT91_MATRIX_MCFG2 [expr {$AT91_MATRIX + 0x08}] ;# Master Configuration Register 2
set AT91_MATRIX_MCFG3 [expr {$AT91_MATRIX + 0x0C}] ;# Master Configuration Register 3
set AT91_MATRIX_MCFG4 [expr {$AT91_MATRIX + 0x10}] ;# Master Configuration Register 4
set AT91_MATRIX_MCFG5 [expr {$AT91_MATRIX + 0x14}] ;# Master Configuration Register 5
set AT91_MATRIX_MCFG6 [expr {$AT91_MATRIX + 0x18}] ;# Master Configuration Register 6
set AT91_MATRIX_MCFG7 [expr {$AT91_MATRIX + 0x1C}] ;# Master Configuration Register 7
set AT91_MATRIX_MCFG8 [expr {$AT91_MATRIX + 0x20}] ;# Master Configuration Register 8
set AT91_MATRIX_ULBT [expr {7 << 0}] ;# Undefined Length Burst Type
set AT91_MATRIX_ULBT_INFINITE [expr {0 << 0}]
set AT91_MATRIX_ULBT_SINGLE [expr {1 << 0}]
set AT91_MATRIX_ULBT_FOUR [expr {2 << 0}]
set AT91_MATRIX_ULBT_EIGHT [expr {3 << 0}]
set AT91_MATRIX_ULBT_SIXTEEN [expr {4 << 0}]
set AT91_MATRIX_SCFG0 [expr ($AT91_MATRIX + 0x40)] ;# Slave Configuration Register 0
set AT91_MATRIX_SCFG1 [expr ($AT91_MATRIX + 0x44)] ;# Slave Configuration Register 1
set AT91_MATRIX_SCFG2 [expr ($AT91_MATRIX + 0x48)] ;# Slave Configuration Register 2
set AT91_MATRIX_SCFG3 [expr ($AT91_MATRIX + 0x4C)] ;# Slave Configuration Register 3
set AT91_MATRIX_SCFG4 [expr ($AT91_MATRIX + 0x50)] ;# Slave Configuration Register 4
set AT91_MATRIX_SCFG5 [expr ($AT91_MATRIX + 0x54)] ;# Slave Configuration Register 5
set AT91_MATRIX_SCFG6 [expr ($AT91_MATRIX + 0x58)] ;# Slave Configuration Register 6
set AT91_MATRIX_SCFG7 [expr ($AT91_MATRIX + 0x5C)] ;# Slave Configuration Register 7
set AT91_MATRIX_SLOT_CYCLE [expr (0xff << 0)] ;# Maximum Number of Allowed Cycles for a Burst
set AT91_MATRIX_DEFMSTR_TYPE [expr (3 << 16)] ;# Default Master Type
set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr (0 << 16)]
set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr (1 << 16)]
set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr (2 << 16)]
set AT91_MATRIX_FIXED_DEFMSTR [expr (0xf << 18)] ;# Fixed Index of Default Master
set AT91_MATRIX_ARBT [expr (3 << 24)] ;# Arbitration Type
set AT91_MATRIX_ARBT_ROUND_ROBIN [expr (0 << 24)]
set AT91_MATRIX_ARBT_FIXED_PRIORITY [expr (1 << 24)]
set AT91_MATRIX_SCFG0 [expr {$AT91_MATRIX + 0x40}] ;# Slave Configuration Register 0
set AT91_MATRIX_SCFG1 [expr {$AT91_MATRIX + 0x44}] ;# Slave Configuration Register 1
set AT91_MATRIX_SCFG2 [expr {$AT91_MATRIX + 0x48}] ;# Slave Configuration Register 2
set AT91_MATRIX_SCFG3 [expr {$AT91_MATRIX + 0x4C}] ;# Slave Configuration Register 3
set AT91_MATRIX_SCFG4 [expr {$AT91_MATRIX + 0x50}] ;# Slave Configuration Register 4
set AT91_MATRIX_SCFG5 [expr {$AT91_MATRIX + 0x54}] ;# Slave Configuration Register 5
set AT91_MATRIX_SCFG6 [expr {$AT91_MATRIX + 0x58}] ;# Slave Configuration Register 6
set AT91_MATRIX_SCFG7 [expr {$AT91_MATRIX + 0x5C}] ;# Slave Configuration Register 7
set AT91_MATRIX_SLOT_CYCLE [expr {0xff << 0}] ;# Maximum Number of Allowed Cycles for a Burst
set AT91_MATRIX_DEFMSTR_TYPE [expr {3 << 16}] ;# Default Master Type
set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr {0 << 16}]
set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr {1 << 16}]
set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr {2 << 16}]
set AT91_MATRIX_FIXED_DEFMSTR [expr {0xf << 18}] ;# Fixed Index of Default Master
set AT91_MATRIX_ARBT [expr {3 << 24}] ;# Arbitration Type
set AT91_MATRIX_ARBT_ROUND_ROBIN [expr {0 << 24}]
set AT91_MATRIX_ARBT_FIXED_PRIORITY [expr {1 << 24}]
set AT91_MATRIX_PRAS0 [expr ($AT91_MATRIX + 0x80)] ;# Priority Register A for Slave 0
set AT91_MATRIX_PRBS0 [expr ($AT91_MATRIX + 0x84)] ;# Priority Register B for Slave 0
set AT91_MATRIX_PRAS1 [expr ($AT91_MATRIX + 0x88)] ;# Priority Register A for Slave 1
set AT91_MATRIX_PRBS1 [expr ($AT91_MATRIX + 0x8C)] ;# Priority Register B for Slave 1
set AT91_MATRIX_PRAS2 [expr ($AT91_MATRIX + 0x90)] ;# Priority Register A for Slave 2
set AT91_MATRIX_PRBS2 [expr ($AT91_MATRIX + 0x94)] ;# Priority Register B for Slave 2
set AT91_MATRIX_PRAS3 [expr ($AT91_MATRIX + 0x98)] ;# Priority Register A for Slave 3
set AT91_MATRIX_PRBS3 [expr ($AT91_MATRIX + 0x9C)] ;# Priority Register B for Slave 3
set AT91_MATRIX_PRAS4 [expr ($AT91_MATRIX + 0xA0)] ;# Priority Register A for Slave 4
set AT91_MATRIX_PRBS4 [expr ($AT91_MATRIX + 0xA4)] ;# Priority Register B for Slave 4
set AT91_MATRIX_PRAS5 [expr ($AT91_MATRIX + 0xA8)] ;# Priority Register A for Slave 5
set AT91_MATRIX_PRBS5 [expr ($AT91_MATRIX + 0xAC)] ;# Priority Register B for Slave 5
set AT91_MATRIX_PRAS6 [expr ($AT91_MATRIX + 0xB0)] ;# Priority Register A for Slave 6
set AT91_MATRIX_PRBS6 [expr ($AT91_MATRIX + 0xB4)] ;# Priority Register B for Slave 6
set AT91_MATRIX_PRAS7 [expr ($AT91_MATRIX + 0xB8)] ;# Priority Register A for Slave 7
set AT91_MATRIX_PRBS7 [expr ($AT91_MATRIX + 0xBC)] ;# Priority Register B for Slave 7
set AT91_MATRIX_M0PR [expr (3 << 0)] ;# Master 0 Priority
set AT91_MATRIX_M1PR [expr (3 << 4)] ;# Master 1 Priority
set AT91_MATRIX_M2PR [expr (3 << 8)] ;# Master 2 Priority
set AT91_MATRIX_M3PR [expr (3 << 12)] ;# Master 3 Priority
set AT91_MATRIX_M4PR [expr (3 << 16)] ;# Master 4 Priority
set AT91_MATRIX_M5PR [expr (3 << 20)] ;# Master 5 Priority
set AT91_MATRIX_M6PR [expr (3 << 24)] ;# Master 6 Priority
set AT91_MATRIX_M7PR [expr (3 << 28)] ;# Master 7 Priority
set AT91_MATRIX_M8PR [expr (3 << 0)] ;# Master 8 Priority (in Register B)
set AT91_MATRIX_PRAS0 [expr {$AT91_MATRIX + 0x80}] ;# Priority Register A for Slave 0
set AT91_MATRIX_PRBS0 [expr {$AT91_MATRIX + 0x84}] ;# Priority Register B for Slave 0
set AT91_MATRIX_PRAS1 [expr {$AT91_MATRIX + 0x88}] ;# Priority Register A for Slave 1
set AT91_MATRIX_PRBS1 [expr {$AT91_MATRIX + 0x8C}] ;# Priority Register B for Slave 1
set AT91_MATRIX_PRAS2 [expr {$AT91_MATRIX + 0x90}] ;# Priority Register A for Slave 2
set AT91_MATRIX_PRBS2 [expr {$AT91_MATRIX + 0x94}] ;# Priority Register B for Slave 2
set AT91_MATRIX_PRAS3 [expr {$AT91_MATRIX + 0x98}] ;# Priority Register A for Slave 3
set AT91_MATRIX_PRBS3 [expr {$AT91_MATRIX + 0x9C}] ;# Priority Register B for Slave 3
set AT91_MATRIX_PRAS4 [expr {$AT91_MATRIX + 0xA0}] ;# Priority Register A for Slave 4
set AT91_MATRIX_PRBS4 [expr {$AT91_MATRIX + 0xA4}] ;# Priority Register B for Slave 4
set AT91_MATRIX_PRAS5 [expr {$AT91_MATRIX + 0xA8}] ;# Priority Register A for Slave 5
set AT91_MATRIX_PRBS5 [expr {$AT91_MATRIX + 0xAC}] ;# Priority Register B for Slave 5
set AT91_MATRIX_PRAS6 [expr {$AT91_MATRIX + 0xB0}] ;# Priority Register A for Slave 6
set AT91_MATRIX_PRBS6 [expr {$AT91_MATRIX + 0xB4}] ;# Priority Register B for Slave 6
set AT91_MATRIX_PRAS7 [expr {$AT91_MATRIX + 0xB8}] ;# Priority Register A for Slave 7
set AT91_MATRIX_PRBS7 [expr {$AT91_MATRIX + 0xBC}] ;# Priority Register B for Slave 7
set AT91_MATRIX_M0PR [expr {3 << 0}] ;# Master 0 Priority
set AT91_MATRIX_M1PR [expr {3 << 4}] ;# Master 1 Priority
set AT91_MATRIX_M2PR [expr {3 << 8}] ;# Master 2 Priority
set AT91_MATRIX_M3PR [expr {3 << 12}] ;# Master 3 Priority
set AT91_MATRIX_M4PR [expr {3 << 16}] ;# Master 4 Priority
set AT91_MATRIX_M5PR [expr {3 << 20}] ;# Master 5 Priority
set AT91_MATRIX_M6PR [expr {3 << 24}] ;# Master 6 Priority
set AT91_MATRIX_M7PR [expr {3 << 28}] ;# Master 7 Priority
set AT91_MATRIX_M8PR [expr {3 << 0}] ;# Master 8 Priority (in Register B)
set AT91_MATRIX_MRCR [expr ($AT91_MATRIX + 0x100)] ;# Master Remap Control Register
set AT91_MATRIX_RCB0 [expr (1 << 0)] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
set AT91_MATRIX_RCB1 [expr (1 << 1)] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
set AT91_MATRIX_RCB2 [expr (1 << 2)]
set AT91_MATRIX_RCB3 [expr (1 << 3)]
set AT91_MATRIX_RCB4 [expr (1 << 4)]
set AT91_MATRIX_RCB5 [expr (1 << 5)]
set AT91_MATRIX_RCB6 [expr (1 << 6)]
set AT91_MATRIX_RCB7 [expr (1 << 7)]
set AT91_MATRIX_RCB8 [expr (1 << 8)]
set AT91_MATRIX_MRCR [expr {$AT91_MATRIX + 0x100}] ;# Master Remap Control Register
set AT91_MATRIX_RCB0 [expr {1 << 0}] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
set AT91_MATRIX_RCB1 [expr {1 << 1}] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
set AT91_MATRIX_RCB2 [expr {1 << 2}]
set AT91_MATRIX_RCB3 [expr {1 << 3}]
set AT91_MATRIX_RCB4 [expr {1 << 4}]
set AT91_MATRIX_RCB5 [expr {1 << 5}]
set AT91_MATRIX_RCB6 [expr {1 << 6}]
set AT91_MATRIX_RCB7 [expr {1 << 7}]
set AT91_MATRIX_RCB8 [expr {1 << 8}]
set AT91_MATRIX_TCMR [expr ($AT91_MATRIX + 0x114)] ;# TCM Configuration Register
set AT91_MATRIX_ITCM_SIZE [expr (0xf << 0)] ;# Size of ITCM enabled memory block
set AT91_MATRIX_ITCM_0 [expr (0 << 0)]
set AT91_MATRIX_ITCM_16 [expr (5 << 0)]
set AT91_MATRIX_ITCM_32 [expr (6 << 0)]
set AT91_MATRIX_DTCM_SIZE [expr (0xf << 4)] ;# Size of DTCM enabled memory block
set AT91_MATRIX_DTCM_0 [expr (0 << 4)]
set AT91_MATRIX_DTCM_16 [expr (5 << 4)]
set AT91_MATRIX_DTCM_32 [expr (6 << 4)]
set AT91_MATRIX_TCMR [expr {$AT91_MATRIX + 0x114}] ;# TCM Configuration Register
set AT91_MATRIX_ITCM_SIZE [expr {0xf << 0}] ;# Size of ITCM enabled memory block
set AT91_MATRIX_ITCM_0 [expr {0 << 0}]
set AT91_MATRIX_ITCM_16 [expr {5 << 0}]
set AT91_MATRIX_ITCM_32 [expr {6 << 0}]
set AT91_MATRIX_DTCM_SIZE [expr {0xf << 4}] ;# Size of DTCM enabled memory block
set AT91_MATRIX_DTCM_0 [expr {0 << 4}]
set AT91_MATRIX_DTCM_16 [expr {5 << 4}]
set AT91_MATRIX_DTCM_32 [expr {6 << 4}]
set AT91_MATRIX_EBI0CSA [expr ($AT91_MATRIX + 0x120)] ;# EBI0 Chip Select Assignment Register
set AT91_MATRIX_EBI0_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment
set AT91_MATRIX_EBI0_CS1A_SMC [expr (0 << 1)]
set AT91_MATRIX_EBI0_CS1A_SDRAMC [expr (1 << 1)]
set AT91_MATRIX_EBI0_CS3A [expr (1 << 3)] ;# Chip Select 3 Assignmen
set AT91_MATRIX_EBI0_CS3A_SMC [expr (0 << 3)]
set AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA [expr (1 << 3)]
set AT91_MATRIX_EBI0_CS4A [expr (1 << 4)] ;# Chip Select 4 Assignment
set AT91_MATRIX_EBI0_CS4A_SMC [expr (0 << 4)]
set AT91_MATRIX_EBI0_CS4A_SMC_CF1 [expr (1 << 4)]
set AT91_MATRIX_EBI0_CS5A [expr (1 << 5)] ;# Chip Select 5 Assignment
set AT91_MATRIX_EBI0_CS5A_SMC [expr (0 << 5)]
set AT91_MATRIX_EBI0_CS5A_SMC_CF2 [expr (1 << 5)]
set AT91_MATRIX_EBI0_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration
set AT91_MATRIX_EBI0_VDDIOMSEL [expr (1 << 16)] ;# Memory voltage selection
set AT91_MATRIX_EBI0_VDDIOMSEL_1_8V [expr (0 << 16)]
set AT91_MATRIX_EBI0_VDDIOMSEL_3_3V [expr (1 << 16)]
set AT91_MATRIX_EBI0CSA [expr {$AT91_MATRIX + 0x120}] ;# EBI0 Chip Select Assignment Register
set AT91_MATRIX_EBI0_CS1A [expr {1 << 1}] ;# Chip Select 1 Assignment
set AT91_MATRIX_EBI0_CS1A_SMC [expr {0 << 1}]
set AT91_MATRIX_EBI0_CS1A_SDRAMC [expr {1 << 1}]
set AT91_MATRIX_EBI0_CS3A [expr {1 << 3}] ;# Chip Select 3 Assignmen
set AT91_MATRIX_EBI0_CS3A_SMC [expr {0 << 3}]
set AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA [expr {1 << 3}]
set AT91_MATRIX_EBI0_CS4A [expr {1 << 4}] ;# Chip Select 4 Assignment
set AT91_MATRIX_EBI0_CS4A_SMC [expr {0 << 4}]
set AT91_MATRIX_EBI0_CS4A_SMC_CF1 [expr {1 << 4}]
set AT91_MATRIX_EBI0_CS5A [expr {1 << 5}] ;# Chip Select 5 Assignment
set AT91_MATRIX_EBI0_CS5A_SMC [expr {0 << 5}]
set AT91_MATRIX_EBI0_CS5A_SMC_CF2 [expr {1 << 5}]
set AT91_MATRIX_EBI0_DBPUC [expr {1 << 8}] ;# Data Bus Pull-up Configuration
set AT91_MATRIX_EBI0_VDDIOMSEL [expr {1 << 16}] ;# Memory voltage selection
set AT91_MATRIX_EBI0_VDDIOMSEL_1_8V [expr {0 << 16}]
set AT91_MATRIX_EBI0_VDDIOMSEL_3_3V [expr {1 << 16}]
set AT91_MATRIX_EBI1CSA [expr ($AT91_MATRIX + 0x124)] ;# EBI1 Chip Select Assignment Register
set AT91_MATRIX_EBI1_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment
set AT91_MATRIX_EBI1_CS1A_SMC [expr (0 << 1)]
set AT91_MATRIX_EBI1_CS1A_SDRAMC [expr (1 << 1)]
set AT91_MATRIX_EBI1_CS2A [expr (1 << 3)] ;# Chip Select 3 Assignment
set AT91_MATRIX_EBI1_CS2A_SMC [expr (0 << 3)]
set AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA [expr (1 << 3)]
set AT91_MATRIX_EBI1_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration
set AT91_MATRIX_EBI1_VDDIOMSEL [expr (1 << 16)] ;# Memory voltage selection
set AT91_MATRIX_EBI1_VDDIOMSEL_1_8V [expr (0 << 16)]
set AT91_MATRIX_EBI1_VDDIOMSEL_3_3V [expr (1 << 16)]
set AT91_MATRIX_EBI1CSA [expr {$AT91_MATRIX + 0x124}] ;# EBI1 Chip Select Assignment Register
set AT91_MATRIX_EBI1_CS1A [expr {1 << 1}] ;# Chip Select 1 Assignment
set AT91_MATRIX_EBI1_CS1A_SMC [expr {0 << 1}]
set AT91_MATRIX_EBI1_CS1A_SDRAMC [expr {1 << 1}]
set AT91_MATRIX_EBI1_CS2A [expr {1 << 3}] ;# Chip Select 3 Assignment
set AT91_MATRIX_EBI1_CS2A_SMC [expr {0 << 3}]
set AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA [expr {1 << 3}]
set AT91_MATRIX_EBI1_DBPUC [expr {1 << 8}] ;# Data Bus Pull-up Configuration
set AT91_MATRIX_EBI1_VDDIOMSEL [expr {1 << 16}] ;# Memory voltage selection
set AT91_MATRIX_EBI1_VDDIOMSEL_1_8V [expr {0 << 16}]
set AT91_MATRIX_EBI1_VDDIOMSEL_3_3V [expr {1 << 16}]

28
tcl/chip/atmel/at91/at91sam9_init.cfg
View File

@@ -12,8 +12,8 @@ proc at91sam9_reset_start { } {
halt
wait_halt 10000
set rstc_mr_val [expr $::AT91_RSTC_KEY]
set rstc_mr_val [expr ($rstc_mr_val | (5 << 8))]
set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}]
set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
mww $::AT91_RSTC_MR $rstc_mr_val ;# RSTC_MR : enable user reset.
}
@@ -21,14 +21,14 @@ proc at91sam9_reset_init { config } {
mww $::AT91_WDT_MR $config(wdt_mr_val) ;# disable watchdog
set ckgr_mor [expr ($::AT91_PMC_MOSCEN | (255 << 8))]
set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}]
mww $::AT91_CKGR_MOR $ckgr_mor ;# CKGR_MOR - enable main osc.
while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 }
set pllar_val [expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog
set pllar_val [expr ($pllar_val | $::AT91_PMC_OUT)]
set pllar_val [expr ($pllar_val | $::AT91_PMC_PLLCOUNT)]
set pllar_val [expr {$pllar_val | $::AT91_PMC_OUT}]
set pllar_val [expr {$pllar_val | $::AT91_PMC_PLLCOUNT}]
set pllar_val [expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)]
set pllar_val [expr ($pllar_val | $config(master_pll_div))]
@@ -37,9 +37,9 @@ proc at91sam9_reset_init { config } {
;# PCK/2 = MCK Master Clock from PLLA
set mckr_val [expr $::AT91_PMC_CSS_PLLA]
set mckr_val [expr ($mckr_val | $::AT91_PMC_PRES_1)]
set mckr_val [expr ($mckr_val | $::AT91SAM9_PMC_MDIV_2)]
set mckr_val [expr ($mckr_val | $::AT91_PMC_PDIV_1)]
set mckr_val [expr {$mckr_val | $::AT91_PMC_PRES_1}]
set mckr_val [expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}]
set mckr_val [expr {$mckr_val | $::AT91_PMC_PDIV_1}]
mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 }
@@ -51,19 +51,19 @@ proc at91sam9_reset_init { config } {
arm7_9 fast_memory_access enable
set rstc_mr_val [expr ($::AT91_RSTC_KEY)]
set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable
if { [info exists config(sdram_piod)] } {
set pdr_addr [expr ($::AT91_PIOD + $::PIO_PDR)]
set pudr_addr [expr ($::AT91_PIOD + $::PIO_PUDR)]
set asr_addr [expr ($::AT91_PIOD + $::PIO_ASR)]
set pdr_addr [expr {$::AT91_PIOD + $::PIO_PDR}]
set pudr_addr [expr {$::AT91_PIOD + $::PIO_PUDR}]
set asr_addr [expr {$::AT91_PIOD + $::PIO_ASR}]
mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
mww $asr_addr 0xffff0000
} else {
set pdr_addr [expr ($::AT91_PIOC + $::PIO_PDR)]
set pudr_addr [expr ($::AT91_PIOC + $::PIO_PUDR)]
set pdr_addr [expr {$::AT91_PIOC + $::PIO_PDR}]
set pudr_addr [expr {$::AT91_PIOC + $::PIO_PUDR}]
mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
}

92
tcl/chip/atmel/at91/at91sam9_sdramc.cfg
View File

@@ -1,7 +1,7 @@
# SDRAM Controller (SDRAMC) registers
set AT91_SDRAMC_MR [expr ($AT91_SDRAMC + 0x00)] ;# SDRAM Controller Mode Register
set AT91_SDRAMC_MODE [expr (0xf << 0)] ;# Command Mode
set AT91_SDRAMC_MR [expr {$AT91_SDRAMC + 0x00}] ;# SDRAM Controller Mode Register
set AT91_SDRAMC_MODE [expr {0xf << 0}] ;# Command Mode
set AT91_SDRAMC_MODE_NORMAL 0
set AT91_SDRAMC_MODE_NOP 1
set AT91_SDRAMC_MODE_PRECHARGE 2
@@ -10,57 +10,57 @@ set AT91_SDRAMC_MODE_REFRESH 4
set AT91_SDRAMC_MODE_EXT_LMR 5
set AT91_SDRAMC_MODE_DEEP 6
set AT91_SDRAMC_TR [expr ($AT91_SDRAMC + 0x04)] ;# SDRAM Controller Refresh Timer Register
set AT91_SDRAMC_COUNT [expr (0xfff << 0)] ;# Refresh Timer Counter
set AT91_SDRAMC_TR [expr {$AT91_SDRAMC + 0x04}] ;# SDRAM Controller Refresh Timer Register
set AT91_SDRAMC_COUNT [expr {0xfff << 0}] ;# Refresh Timer Counter
set AT91_SDRAMC_CR [expr ($AT91_SDRAMC + 0x08)] ;# SDRAM Controller Configuration Register
set AT91_SDRAMC_NC [expr (3 << 0)] ;# Number of Column Bits
set AT91_SDRAMC_NC_8 [expr (0 << 0)]
set AT91_SDRAMC_NC_9 [expr (1 << 0)]
set AT91_SDRAMC_NC_10 [expr (2 << 0)]
set AT91_SDRAMC_NC_11 [expr (3 << 0)]
set AT91_SDRAMC_NR [expr (3 << 2)] ;# Number of Row Bits
set AT91_SDRAMC_NR_11 [expr (0 << 2)]
set AT91_SDRAMC_NR_12 [expr (1 << 2)]
set AT91_SDRAMC_NR_13 [expr (2 << 2)]
set AT91_SDRAMC_NB [expr (1 << 4)] ;# Number of Banks
set AT91_SDRAMC_NB_2 [expr (0 << 4)]
set AT91_SDRAMC_NB_4 [expr (1 << 4)]
set AT91_SDRAMC_CAS [expr (3 << 5)] ;# CAS Latency
set AT91_SDRAMC_CAS_1 [expr (1 << 5)]
set AT91_SDRAMC_CAS_2 [expr (2 << 5)]
set AT91_SDRAMC_CAS_3 [expr (3 << 5)]
set AT91_SDRAMC_DBW [expr (1 << 7)] ;# Data Bus Width
set AT91_SDRAMC_DBW_32 [expr (0 << 7)]
set AT91_SDRAMC_DBW_16 [expr (1 << 7)]
set AT91_SDRAMC_TWR [expr (0xf << 8)] ;# Write Recovery Delay
set AT91_SDRAMC_TRC [expr (0xf << 12)] ;# Row Cycle Delay
set AT91_SDRAMC_TRP [expr (0xf << 16)] ;# Row Precharge Delay
set AT91_SDRAMC_TRCD [expr (0xf << 20)] ;# Row to Column Delay
set AT91_SDRAMC_TRAS [expr (0xf << 24)] ;# Active to Precharge Delay
set AT91_SDRAMC_TXSR [expr (0xf << 28)] ;# Exit Self Refresh to Active Delay
set AT91_SDRAMC_CR [expr {$AT91_SDRAMC + 0x08}] ;# SDRAM Controller Configuration Register
set AT91_SDRAMC_NC [expr {3 << 0}] ;# Number of Column Bits
set AT91_SDRAMC_NC_8 [expr {0 << 0}]
set AT91_SDRAMC_NC_9 [expr {1 << 0}]
set AT91_SDRAMC_NC_10 [expr {2 << 0}]
set AT91_SDRAMC_NC_11 [expr {3 << 0}]
set AT91_SDRAMC_NR [expr {3 << 2}] ;# Number of Row Bits
set AT91_SDRAMC_NR_11 [expr {0 << 2}]
set AT91_SDRAMC_NR_12 [expr {1 << 2}]
set AT91_SDRAMC_NR_13 [expr {2 << 2}]
set AT91_SDRAMC_NB [expr {1 << 4}] ;# Number of Banks
set AT91_SDRAMC_NB_2 [expr {0 << 4}]
set AT91_SDRAMC_NB_4 [expr {1 << 4}]
set AT91_SDRAMC_CAS [expr {3 << 5}] ;# CAS Latency
set AT91_SDRAMC_CAS_1 [expr {1 << 5}]
set AT91_SDRAMC_CAS_2 [expr {2 << 5}]
set AT91_SDRAMC_CAS_3 [expr {3 << 5}]
set AT91_SDRAMC_DBW [expr {1 << 7}] ;# Data Bus Width
set AT91_SDRAMC_DBW_32 [expr {0 << 7}]
set AT91_SDRAMC_DBW_16 [expr {1 << 7}]
set AT91_SDRAMC_TWR [expr {0xf << 8}] ;# Write Recovery Delay
set AT91_SDRAMC_TRC [expr {0xf << 12}] ;# Row Cycle Delay
set AT91_SDRAMC_TRP [expr {0xf << 16}] ;# Row Precharge Delay
set AT91_SDRAMC_TRCD [expr {0xf << 20}] ;# Row to Column Delay
set AT91_SDRAMC_TRAS [expr {0xf << 24}] ;# Active to Precharge Delay
set AT91_SDRAMC_TXSR [expr {0xf << 28}] ;# Exit Self Refresh to Active Delay
set AT91_SDRAMC_LPR [expr ($AT91_SDRAMC + 0x10)] ;# SDRAM Controller Low Power Register
set AT91_SDRAMC_LPCB [expr (3 << 0)] ;# Low-power Configurations
set AT91_SDRAMC_LPR [expr {$AT91_SDRAMC + 0x10}] ;# SDRAM Controller Low Power Register
set AT91_SDRAMC_LPCB [expr {3 << 0}] ;# Low-power Configurations
set AT91_SDRAMC_LPCB_DISABLE 0
set AT91_SDRAMC_LPCB_SELF_REFRESH 1
set AT91_SDRAMC_LPCB_POWER_DOWN 2
set AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
set AT91_SDRAMC_PASR [expr (7 << 4)] ;# Partial Array Self Refresh
set AT91_SDRAMC_TCSR [expr (3 << 8)] ;# Temperature Compensated Self Refresh
set AT91_SDRAMC_DS [expr (3 << 10)] ;# Drive Strength
set AT91_SDRAMC_TIMEOUT [expr (3 << 12)] ;# Time to define when Low Power Mode is enabled
set AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr (0 << 12)]
set AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr (1 << 12)]
set AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr (2 << 12)]
set AT91_SDRAMC_PASR [expr {7 << 4}] ;# Partial Array Self Refresh
set AT91_SDRAMC_TCSR [expr {3 << 8}] ;# Temperature Compensated Self Refresh
set AT91_SDRAMC_DS [expr {3 << 10}] ;# Drive Strength
set AT91_SDRAMC_TIMEOUT [expr {3 << 12}] ;# Time to define when Low Power Mode is enabled
set AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr {0 << 12}]
set AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr {1 << 12}]
set AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr {2 << 12}]
set AT91_SDRAMC_IER [expr ($AT91_SDRAMC + 0x14)] ;# SDRAM Controller Interrupt Enable Register
set AT91_SDRAMC_IDR [expr ($AT91_SDRAMC + 0x18)] ;# SDRAM Controller Interrupt Disable Register
set AT91_SDRAMC_IMR [expr ($AT91_SDRAMC + 0x1C)] ;# SDRAM Controller Interrupt Mask Register
set AT91_SDRAMC_ISR [expr ($AT91_SDRAMC + 0x20)] ;# SDRAM Controller Interrupt Status Register
set AT91_SDRAMC_RES [expr (1 << 0)] ;# Refresh Error Status
set AT91_SDRAMC_IER [expr {$AT91_SDRAMC + 0x14}] ;# SDRAM Controller Interrupt Enable Register
set AT91_SDRAMC_IDR [expr {$AT91_SDRAMC + 0x18}] ;# SDRAM Controller Interrupt Disable Register
set AT91_SDRAMC_IMR [expr {$AT91_SDRAMC + 0x1C}] ;# SDRAM Controller Interrupt Mask Register
set AT91_SDRAMC_ISR [expr {$AT91_SDRAMC + 0x20}] ;# SDRAM Controller Interrupt Status Register
set AT91_SDRAMC_RES [expr {1 << 0}] ;# Refresh Error Status
set AT91_SDRAMC_MDR [expr ($AT91_SDRAMC + 0x24)] ;# SDRAM Memory Device Register
set AT91_SDRAMC_MD [expr (3 << 0)] ;# Memory Device Type
set AT91_SDRAMC_MDR [expr {$AT91_SDRAMC + 0x24}] ;# SDRAM Memory Device Register
set AT91_SDRAMC_MD [expr {3 << 0}] ;# Memory Device Type
set AT91_SDRAMC_MD_SDRAM 0
set AT91_SDRAMC_MD_LOW_POWER_SDRAM 1

40
tcl/chip/atmel/at91/at91sam9_smc.cfg
View File

@@ -1,20 +1,20 @@
set AT91_SMC_READMODE [expr (1 << 0)] ;# Read Mode
set AT91_SMC_WRITEMODE [expr (1 << 1)] ;# Write Mode
set AT91_SMC_EXNWMODE [expr (3 << 4)] ;# NWAIT Mode
set AT91_SMC_EXNWMODE_DISABLE [expr (0 << 4)]
set AT91_SMC_EXNWMODE_FROZEN [expr (2 << 4)]
set AT91_SMC_EXNWMODE_READY [expr (3 << 4)]
set AT91_SMC_BAT [expr (1 << 8)] ;# Byte Access Type
set AT91_SMC_BAT_SELECT [expr (0 << 8)]
set AT91_SMC_BAT_WRITE [expr (1 << 8)]
set AT91_SMC_DBW [expr (3 << 12)] ;# Data Bus Width */
set AT91_SMC_DBW_8 [expr (0 << 12)]
set AT91_SMC_DBW_16 [expr (1 << 12)]
set AT91_SMC_DBW_32 [expr (2 << 12)]
set AT91_SMC_TDFMODE [expr (1 << 20)] ;# TDF Optimization - Enabled
set AT91_SMC_PMEN [expr (1 << 24)] ;# Page Mode Enabled
set AT91_SMC_PS [expr (3 << 28)] ;# Page Size
set AT91_SMC_PS_4 [expr (0 << 28)]
set AT91_SMC_PS_8 [expr (1 << 28)]
set AT91_SMC_PS_16 [expr (2 << 28)]
set AT91_SMC_PS_32 [expr (3 << 28)]
set AT91_SMC_READMODE [expr {1 << 0}] ;# Read Mode
set AT91_SMC_WRITEMODE [expr {1 << 1}] ;# Write Mode
set AT91_SMC_EXNWMODE [expr {3 << 4}] ;# NWAIT Mode
set AT91_SMC_EXNWMODE_DISABLE [expr {0 << 4}]
set AT91_SMC_EXNWMODE_FROZEN [expr {2 << 4}]
set AT91_SMC_EXNWMODE_READY [expr {3 << 4}]
set AT91_SMC_BAT [expr {1 << 8}] ;# Byte Access Type
set AT91_SMC_BAT_SELECT [expr {0 << 8}]
set AT91_SMC_BAT_WRITE [expr {1 << 8}]
set AT91_SMC_DBW [expr {3 << 12}] ;# Data Bus Width */
set AT91_SMC_DBW_8 [expr {0 << 12}]
set AT91_SMC_DBW_16 [expr {1 << 12}]
set AT91_SMC_DBW_32 [expr {2 << 12}]
set AT91_SMC_TDFMODE [expr {1 << 20}] ;# TDF Optimization - Enabled
set AT91_SMC_PMEN [expr {1 << 24}] ;# Page Mode Enabled
set AT91_SMC_PS [expr {3 << 28}] ;# Page Size
set AT91_SMC_PS_4 [expr {0 << 28}]
set AT91_SMC_PS_8 [expr {1 << 28}]
set AT91_SMC_PS_16 [expr {2 << 28}]
set AT91_SMC_PS_32 [expr {3 << 28}]

10
tcl/chip/atmel/at91/rtt.tcl
View File

@@ -1,15 +1,15 @@
set RTTC_RTMR [expr $AT91C_BASE_RTTC + 0x00]
set RTTC_RTAR [expr $AT91C_BASE_RTTC + 0x04]
set RTTC_RTVR [expr $AT91C_BASE_RTTC + 0x08]
set RTTC_RTSR [expr $AT91C_BASE_RTTC + 0x0c]
set RTTC_RTMR [expr {$AT91C_BASE_RTTC + 0x00}]
set RTTC_RTAR [expr {$AT91C_BASE_RTTC + 0x04}]
set RTTC_RTVR [expr {$AT91C_BASE_RTTC + 0x08}]
set RTTC_RTSR [expr {$AT91C_BASE_RTTC + 0x0c}]
global RTTC_RTMR
global RTTC_RTAR
global RTTC_RTVR
global RTTC_RTSR
proc show_RTTC_RTMR_helper { NAME ADDR VAL } {
set rtpres [expr $VAL & 0x0ffff]
set rtpres [expr {$VAL & 0x0ffff}]
global BIT16 BIT17
if { $rtpres == 0 } {
set rtpres 65536;

26
tcl/chip/atmel/at91/usarts.tcl
View File

@@ -1,20 +1,20 @@
# the DBGU and USARTs are 'almost' indentical'
set DBGU_CR [expr $AT91C_BASE_DBGU + 0x00000000]
set DBGU_MR [expr $AT91C_BASE_DBGU + 0x00000004]
set DBGU_IER [expr $AT91C_BASE_DBGU + 0x00000008]
set DBGU_IDR [expr $AT91C_BASE_DBGU + 0x0000000C]
set DBGU_IMR [expr $AT91C_BASE_DBGU + 0x00000010]
set DBGU_CSR [expr $AT91C_BASE_DBGU + 0x00000014]
set DBGU_RHR [expr $AT91C_BASE_DBGU + 0x00000018]
set DBGU_THR [expr $AT91C_BASE_DBGU + 0x0000001C]
set DBGU_BRGR [expr $AT91C_BASE_DBGU + 0x00000020]
set DBGU_CR [expr {$AT91C_BASE_DBGU + 0x00000000}]
set DBGU_MR [expr {$AT91C_BASE_DBGU + 0x00000004}]
set DBGU_IER [expr {$AT91C_BASE_DBGU + 0x00000008}]
set DBGU_IDR [expr {$AT91C_BASE_DBGU + 0x0000000C}]
set DBGU_IMR [expr {$AT91C_BASE_DBGU + 0x00000010}]
set DBGU_CSR [expr {$AT91C_BASE_DBGU + 0x00000014}]
set DBGU_RHR [expr {$AT91C_BASE_DBGU + 0x00000018}]
set DBGU_THR [expr {$AT91C_BASE_DBGU + 0x0000001C}]
set DBGU_BRGR [expr {$AT91C_BASE_DBGU + 0x00000020}]
# no RTOR
# no TTGR
# no FIDI
# no NER
set DBGU_CIDR [expr $AT91C_BASE_DBGU + 0x00000040]
set DBGU_EXID [expr $AT91C_BASE_DBGU + 0x00000044]
set DBGU_FNTR [expr $AT91C_BASE_DBGU + 0x00000048]
set DBGU_CIDR [expr {$AT91C_BASE_DBGU + 0x00000040}]
set DBGU_EXID [expr {$AT91C_BASE_DBGU + 0x00000044}]
set DBGU_FNTR [expr {$AT91C_BASE_DBGU + 0x00000048}]
set USx_CR 0x00000000
@@ -54,7 +54,7 @@ proc show_mmr_USx_MR_helper { NAME ADDR VAL } {
2 { set s "Force=0" }
3 { set s "Force=1" }
* {
set $x [expr $x & 6]
set $x [expr {$x & 6}]
switch -exact $x {
4 { set s "None" }
6 { set s "Multidrop Mode" }