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tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change

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Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

In the TCL scripts distributed with OpenOCD there are 1700+ lines
that should be modified before switching to jimtcl 0.81.

Apply the script below on every script in tcl folder. It fixes
more than 92% of the lines

%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
 #!/usr/bin/perl -Wpi

 my $re_sym = qr{[a-z_][a-z0-9_]*}i;
 my $re_var = qr{(?:\$|\$::)$re_sym};
 my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i;
 my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)};
 my $re_op = qr{<<|>>|[+\-*/&|]};
 my $re_expr = qr{(
     (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item)
     \s*$re_op\s*
     (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\))
 )}x;

 # [expr [dict get $regsC100 SYM] + HEXNUM]
 s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/;

 # [ expr (EXPR) ]
 # [ expr EXPR ]
 # note: $re_expr captures '$3'
 s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/;
 s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/;
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---

Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6159
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo
2021-04-10 01:23:57 +02:00
parent 82b6a41117
commit f5657aa76e
61 changed files with 1592 additions and 1592 deletions
Download Patch File Download Diff File Expand all files Collapse all files

92
tcl/chip/atmel/at91/at91sam9_sdramc.cfg
View File

@@ -1,7 +1,7 @@
# SDRAM Controller (SDRAMC) registers
set AT91_SDRAMC_MR [expr ($AT91_SDRAMC + 0x00)] ;# SDRAM Controller Mode Register
set AT91_SDRAMC_MODE [expr (0xf << 0)] ;# Command Mode
set AT91_SDRAMC_MR [expr {$AT91_SDRAMC + 0x00}] ;# SDRAM Controller Mode Register
set AT91_SDRAMC_MODE [expr {0xf << 0}] ;# Command Mode
set AT91_SDRAMC_MODE_NORMAL 0
set AT91_SDRAMC_MODE_NOP 1
set AT91_SDRAMC_MODE_PRECHARGE 2
@@ -10,57 +10,57 @@ set AT91_SDRAMC_MODE_REFRESH 4
set AT91_SDRAMC_MODE_EXT_LMR 5
set AT91_SDRAMC_MODE_DEEP 6
set AT91_SDRAMC_TR [expr ($AT91_SDRAMC + 0x04)] ;# SDRAM Controller Refresh Timer Register
set AT91_SDRAMC_COUNT [expr (0xfff << 0)] ;# Refresh Timer Counter
set AT91_SDRAMC_TR [expr {$AT91_SDRAMC + 0x04}] ;# SDRAM Controller Refresh Timer Register
set AT91_SDRAMC_COUNT [expr {0xfff << 0}] ;# Refresh Timer Counter
set AT91_SDRAMC_CR [expr ($AT91_SDRAMC + 0x08)] ;# SDRAM Controller Configuration Register
set AT91_SDRAMC_NC [expr (3 << 0)] ;# Number of Column Bits
set AT91_SDRAMC_NC_8 [expr (0 << 0)]
set AT91_SDRAMC_NC_9 [expr (1 << 0)]
set AT91_SDRAMC_NC_10 [expr (2 << 0)]
set AT91_SDRAMC_NC_11 [expr (3 << 0)]
set AT91_SDRAMC_NR [expr (3 << 2)] ;# Number of Row Bits
set AT91_SDRAMC_NR_11 [expr (0 << 2)]
set AT91_SDRAMC_NR_12 [expr (1 << 2)]
set AT91_SDRAMC_NR_13 [expr (2 << 2)]
set AT91_SDRAMC_NB [expr (1 << 4)] ;# Number of Banks
set AT91_SDRAMC_NB_2 [expr (0 << 4)]
set AT91_SDRAMC_NB_4 [expr (1 << 4)]
set AT91_SDRAMC_CAS [expr (3 << 5)] ;# CAS Latency
set AT91_SDRAMC_CAS_1 [expr (1 << 5)]
set AT91_SDRAMC_CAS_2 [expr (2 << 5)]
set AT91_SDRAMC_CAS_3 [expr (3 << 5)]
set AT91_SDRAMC_DBW [expr (1 << 7)] ;# Data Bus Width
set AT91_SDRAMC_DBW_32 [expr (0 << 7)]
set AT91_SDRAMC_DBW_16 [expr (1 << 7)]
set AT91_SDRAMC_TWR [expr (0xf << 8)] ;# Write Recovery Delay
set AT91_SDRAMC_TRC [expr (0xf << 12)] ;# Row Cycle Delay
set AT91_SDRAMC_TRP [expr (0xf << 16)] ;# Row Precharge Delay
set AT91_SDRAMC_TRCD [expr (0xf << 20)] ;# Row to Column Delay
set AT91_SDRAMC_TRAS [expr (0xf << 24)] ;# Active to Precharge Delay
set AT91_SDRAMC_TXSR [expr (0xf << 28)] ;# Exit Self Refresh to Active Delay
set AT91_SDRAMC_CR [expr {$AT91_SDRAMC + 0x08}] ;# SDRAM Controller Configuration Register
set AT91_SDRAMC_NC [expr {3 << 0}] ;# Number of Column Bits
set AT91_SDRAMC_NC_8 [expr {0 << 0}]
set AT91_SDRAMC_NC_9 [expr {1 << 0}]
set AT91_SDRAMC_NC_10 [expr {2 << 0}]
set AT91_SDRAMC_NC_11 [expr {3 << 0}]
set AT91_SDRAMC_NR [expr {3 << 2}] ;# Number of Row Bits
set AT91_SDRAMC_NR_11 [expr {0 << 2}]
set AT91_SDRAMC_NR_12 [expr {1 << 2}]
set AT91_SDRAMC_NR_13 [expr {2 << 2}]
set AT91_SDRAMC_NB [expr {1 << 4}] ;# Number of Banks
set AT91_SDRAMC_NB_2 [expr {0 << 4}]
set AT91_SDRAMC_NB_4 [expr {1 << 4}]
set AT91_SDRAMC_CAS [expr {3 << 5}] ;# CAS Latency
set AT91_SDRAMC_CAS_1 [expr {1 << 5}]
set AT91_SDRAMC_CAS_2 [expr {2 << 5}]
set AT91_SDRAMC_CAS_3 [expr {3 << 5}]
set AT91_SDRAMC_DBW [expr {1 << 7}] ;# Data Bus Width
set AT91_SDRAMC_DBW_32 [expr {0 << 7}]
set AT91_SDRAMC_DBW_16 [expr {1 << 7}]
set AT91_SDRAMC_TWR [expr {0xf << 8}] ;# Write Recovery Delay
set AT91_SDRAMC_TRC [expr {0xf << 12}] ;# Row Cycle Delay
set AT91_SDRAMC_TRP [expr {0xf << 16}] ;# Row Precharge Delay
set AT91_SDRAMC_TRCD [expr {0xf << 20}] ;# Row to Column Delay
set AT91_SDRAMC_TRAS [expr {0xf << 24}] ;# Active to Precharge Delay
set AT91_SDRAMC_TXSR [expr {0xf << 28}] ;# Exit Self Refresh to Active Delay
set AT91_SDRAMC_LPR [expr ($AT91_SDRAMC + 0x10)] ;# SDRAM Controller Low Power Register
set AT91_SDRAMC_LPCB [expr (3 << 0)] ;# Low-power Configurations
set AT91_SDRAMC_LPR [expr {$AT91_SDRAMC + 0x10}] ;# SDRAM Controller Low Power Register
set AT91_SDRAMC_LPCB [expr {3 << 0}] ;# Low-power Configurations
set AT91_SDRAMC_LPCB_DISABLE 0
set AT91_SDRAMC_LPCB_SELF_REFRESH 1
set AT91_SDRAMC_LPCB_POWER_DOWN 2
set AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
set AT91_SDRAMC_PASR [expr (7 << 4)] ;# Partial Array Self Refresh
set AT91_SDRAMC_TCSR [expr (3 << 8)] ;# Temperature Compensated Self Refresh
set AT91_SDRAMC_DS [expr (3 << 10)] ;# Drive Strength
set AT91_SDRAMC_TIMEOUT [expr (3 << 12)] ;# Time to define when Low Power Mode is enabled
set AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr (0 << 12)]
set AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr (1 << 12)]
set AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr (2 << 12)]
set AT91_SDRAMC_PASR [expr {7 << 4}] ;# Partial Array Self Refresh
set AT91_SDRAMC_TCSR [expr {3 << 8}] ;# Temperature Compensated Self Refresh
set AT91_SDRAMC_DS [expr {3 << 10}] ;# Drive Strength
set AT91_SDRAMC_TIMEOUT [expr {3 << 12}] ;# Time to define when Low Power Mode is enabled
set AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr {0 << 12}]
set AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr {1 << 12}]
set AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr {2 << 12}]
set AT91_SDRAMC_IER [expr ($AT91_SDRAMC + 0x14)] ;# SDRAM Controller Interrupt Enable Register
set AT91_SDRAMC_IDR [expr ($AT91_SDRAMC + 0x18)] ;# SDRAM Controller Interrupt Disable Register
set AT91_SDRAMC_IMR [expr ($AT91_SDRAMC + 0x1C)] ;# SDRAM Controller Interrupt Mask Register
set AT91_SDRAMC_ISR [expr ($AT91_SDRAMC + 0x20)] ;# SDRAM Controller Interrupt Status Register
set AT91_SDRAMC_RES [expr (1 << 0)] ;# Refresh Error Status
set AT91_SDRAMC_IER [expr {$AT91_SDRAMC + 0x14}] ;# SDRAM Controller Interrupt Enable Register
set AT91_SDRAMC_IDR [expr {$AT91_SDRAMC + 0x18}] ;# SDRAM Controller Interrupt Disable Register
set AT91_SDRAMC_IMR [expr {$AT91_SDRAMC + 0x1C}] ;# SDRAM Controller Interrupt Mask Register
set AT91_SDRAMC_ISR [expr {$AT91_SDRAMC + 0x20}] ;# SDRAM Controller Interrupt Status Register
set AT91_SDRAMC_RES [expr {1 << 0}] ;# Refresh Error Status
set AT91_SDRAMC_MDR [expr ($AT91_SDRAMC + 0x24)] ;# SDRAM Memory Device Register
set AT91_SDRAMC_MD [expr (3 << 0)] ;# Memory Device Type
set AT91_SDRAMC_MDR [expr {$AT91_SDRAMC + 0x24}] ;# SDRAM Memory Device Register
set AT91_SDRAMC_MD [expr {3 << 0}] ;# Memory Device Type
set AT91_SDRAMC_MD_SDRAM 0
set AT91_SDRAMC_MD_LOW_POWER_SDRAM 1