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tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change

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Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

In the TCL scripts distributed with OpenOCD there are 1700+ lines
that should be modified before switching to jimtcl 0.81.

Apply the script below on every script in tcl folder. It fixes
more than 92% of the lines

%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
 #!/usr/bin/perl -Wpi

 my $re_sym = qr{[a-z_][a-z0-9_]*}i;
 my $re_var = qr{(?:\$|\$::)$re_sym};
 my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i;
 my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)};
 my $re_op = qr{<<|>>|[+\-*/&|]};
 my $re_expr = qr{(
     (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item)
     \s*$re_op\s*
     (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\))
 )}x;

 # [expr [dict get $regsC100 SYM] + HEXNUM]
 s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/;

 # [ expr (EXPR) ]
 # [ expr EXPR ]
 # note: $re_expr captures '$3'
 s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/;
 s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/;
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---

Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6159
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo
2021-04-10 01:23:57 +02:00
parent 82b6a41117
commit f5657aa76e
61 changed files with 1592 additions and 1592 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
tcl/chip/st/stm32/stm32_rcc.tcl
View File

@@ -1,14 +1,14 @@
set RCC_CR [expr $RCC_BASE + 0x00]
set RCC_CFGR [expr $RCC_BASE + 0x04]
set RCC_CIR [expr $RCC_BASE + 0x08]
set RCC_APB2RSTR [expr $RCC_BASE + 0x0c]
set RCC_APB1RSTR [expr $RCC_BASE + 0x10]
set RCC_AHBENR [expr $RCC_BASE + 0x14]
set RCC_APB2ENR [expr $RCC_BASE + 0x18]
set RCC_APB1ENR [expr $RCC_BASE + 0x1c]
set RCC_BDCR [expr $RCC_BASE + 0x20]
set RCC_CSR [expr $RCC_BASE + 0x24]
set RCC_CR [expr {$RCC_BASE + 0x00}]
set RCC_CFGR [expr {$RCC_BASE + 0x04}]
set RCC_CIR [expr {$RCC_BASE + 0x08}]
set RCC_APB2RSTR [expr {$RCC_BASE + 0x0c}]
set RCC_APB1RSTR [expr {$RCC_BASE + 0x10}]
set RCC_AHBENR [expr {$RCC_BASE + 0x14}]
set RCC_APB2ENR [expr {$RCC_BASE + 0x18}]
set RCC_APB1ENR [expr {$RCC_BASE + 0x1c}]
set RCC_BDCR [expr {$RCC_BASE + 0x20}]
set RCC_CSR [expr {$RCC_BASE + 0x24}]
proc show_RCC_CR { } {

130
tcl/chip/st/stm32/stm32_regs.tcl
View File

@@ -11,78 +11,78 @@ set FSMC_R_BASE 0xA0000000
# /*Peripheral memory map */
set APB1PERIPH_BASE [set PERIPH_BASE]
set APB2PERIPH_BASE [expr $PERIPH_BASE + 0x10000]
set AHBPERIPH_BASE [expr $PERIPH_BASE + 0x20000]
set APB2PERIPH_BASE [expr {$PERIPH_BASE + 0x10000}]
set AHBPERIPH_BASE [expr {$PERIPH_BASE + 0x20000}]
set TIM2_BASE [expr $APB1PERIPH_BASE + 0x0000]
set TIM3_BASE [expr $APB1PERIPH_BASE + 0x0400]
set TIM4_BASE [expr $APB1PERIPH_BASE + 0x0800]
set TIM5_BASE [expr $APB1PERIPH_BASE + 0x0C00]
set TIM6_BASE [expr $APB1PERIPH_BASE + 0x1000]
set TIM7_BASE [expr $APB1PERIPH_BASE + 0x1400]
set RTC_BASE [expr $APB1PERIPH_BASE + 0x2800]
set WWDG_BASE [expr $APB1PERIPH_BASE + 0x2C00]
set IWDG_BASE [expr $APB1PERIPH_BASE + 0x3000]
set SPI2_BASE [expr $APB1PERIPH_BASE + 0x3800]
set SPI3_BASE [expr $APB1PERIPH_BASE + 0x3C00]
set USART2_BASE [expr $APB1PERIPH_BASE + 0x4400]
set USART3_BASE [expr $APB1PERIPH_BASE + 0x4800]
set UART4_BASE [expr $APB1PERIPH_BASE + 0x4C00]
set UART5_BASE [expr $APB1PERIPH_BASE + 0x5000]
set I2C1_BASE [expr $APB1PERIPH_BASE + 0x5400]
set I2C2_BASE [expr $APB1PERIPH_BASE + 0x5800]
set CAN_BASE [expr $APB1PERIPH_BASE + 0x6400]
set BKP_BASE [expr $APB1PERIPH_BASE + 0x6C00]
set PWR_BASE [expr $APB1PERIPH_BASE + 0x7000]
set DAC_BASE [expr $APB1PERIPH_BASE + 0x7400]
set TIM2_BASE [expr {$APB1PERIPH_BASE + 0x0000}]
set TIM3_BASE [expr {$APB1PERIPH_BASE + 0x0400}]
set TIM4_BASE [expr {$APB1PERIPH_BASE + 0x0800}]
set TIM5_BASE [expr {$APB1PERIPH_BASE + 0x0C00}]
set TIM6_BASE [expr {$APB1PERIPH_BASE + 0x1000}]
set TIM7_BASE [expr {$APB1PERIPH_BASE + 0x1400}]
set RTC_BASE [expr {$APB1PERIPH_BASE + 0x2800}]
set WWDG_BASE [expr {$APB1PERIPH_BASE + 0x2C00}]
set IWDG_BASE [expr {$APB1PERIPH_BASE + 0x3000}]
set SPI2_BASE [expr {$APB1PERIPH_BASE + 0x3800}]
set SPI3_BASE [expr {$APB1PERIPH_BASE + 0x3C00}]
set USART2_BASE [expr {$APB1PERIPH_BASE + 0x4400}]
set USART3_BASE [expr {$APB1PERIPH_BASE + 0x4800}]
set UART4_BASE [expr {$APB1PERIPH_BASE + 0x4C00}]
set UART5_BASE [expr {$APB1PERIPH_BASE + 0x5000}]
set I2C1_BASE [expr {$APB1PERIPH_BASE + 0x5400}]
set I2C2_BASE [expr {$APB1PERIPH_BASE + 0x5800}]
set CAN_BASE [expr {$APB1PERIPH_BASE + 0x6400}]
set BKP_BASE [expr {$APB1PERIPH_BASE + 0x6C00}]
set PWR_BASE [expr {$APB1PERIPH_BASE + 0x7000}]
set DAC_BASE [expr {$APB1PERIPH_BASE + 0x7400}]
set AFIO_BASE [expr $APB2PERIPH_BASE + 0x0000]
set EXTI_BASE [expr $APB2PERIPH_BASE + 0x0400]
set GPIOA_BASE [expr $APB2PERIPH_BASE + 0x0800]
set GPIOB_BASE [expr $APB2PERIPH_BASE + 0x0C00]
set GPIOC_BASE [expr $APB2PERIPH_BASE + 0x1000]
set GPIOD_BASE [expr $APB2PERIPH_BASE + 0x1400]
set GPIOE_BASE [expr $APB2PERIPH_BASE + 0x1800]
set GPIOF_BASE [expr $APB2PERIPH_BASE + 0x1C00]
set GPIOG_BASE [expr $APB2PERIPH_BASE + 0x2000]
set ADC1_BASE [expr $APB2PERIPH_BASE + 0x2400]
set ADC2_BASE [expr $APB2PERIPH_BASE + 0x2800]
set TIM1_BASE [expr $APB2PERIPH_BASE + 0x2C00]
set SPI1_BASE [expr $APB2PERIPH_BASE + 0x3000]
set TIM8_BASE [expr $APB2PERIPH_BASE + 0x3400]
set USART1_BASE [expr $APB2PERIPH_BASE + 0x3800]
set ADC3_BASE [expr $APB2PERIPH_BASE + 0x3C00]
set AFIO_BASE [expr {$APB2PERIPH_BASE + 0x0000}]
set EXTI_BASE [expr {$APB2PERIPH_BASE + 0x0400}]
set GPIOA_BASE [expr {$APB2PERIPH_BASE + 0x0800}]
set GPIOB_BASE [expr {$APB2PERIPH_BASE + 0x0C00}]
set GPIOC_BASE [expr {$APB2PERIPH_BASE + 0x1000}]
set GPIOD_BASE [expr {$APB2PERIPH_BASE + 0x1400}]
set GPIOE_BASE [expr {$APB2PERIPH_BASE + 0x1800}]
set GPIOF_BASE [expr {$APB2PERIPH_BASE + 0x1C00}]
set GPIOG_BASE [expr {$APB2PERIPH_BASE + 0x2000}]
set ADC1_BASE [expr {$APB2PERIPH_BASE + 0x2400}]
set ADC2_BASE [expr {$APB2PERIPH_BASE + 0x2800}]
set TIM1_BASE [expr {$APB2PERIPH_BASE + 0x2C00}]
set SPI1_BASE [expr {$APB2PERIPH_BASE + 0x3000}]
set TIM8_BASE [expr {$APB2PERIPH_BASE + 0x3400}]
set USART1_BASE [expr {$APB2PERIPH_BASE + 0x3800}]
set ADC3_BASE [expr {$APB2PERIPH_BASE + 0x3C00}]
set SDIO_BASE [expr $PERIPH_BASE + 0x18000]
set SDIO_BASE [expr {$PERIPH_BASE + 0x18000}]
set DMA1_BASE [expr $AHBPERIPH_BASE + 0x0000]
set DMA1_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0008]
set DMA1_Channel2_BASE [expr $AHBPERIPH_BASE + 0x001C]
set DMA1_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0030]
set DMA1_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0044]
set DMA1_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0058]
set DMA1_Channel6_BASE [expr $AHBPERIPH_BASE + 0x006C]
set DMA1_Channel7_BASE [expr $AHBPERIPH_BASE + 0x0080]
set DMA2_BASE [expr $AHBPERIPH_BASE + 0x0400]
set DMA2_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0408]
set DMA2_Channel2_BASE [expr $AHBPERIPH_BASE + 0x041C]
set DMA2_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0430]
set DMA2_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0444]
set DMA2_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0458]
set RCC_BASE [expr $AHBPERIPH_BASE + 0x1000]
set CRC_BASE [expr $AHBPERIPH_BASE + 0x3000]
set DMA1_BASE [expr {$AHBPERIPH_BASE + 0x0000}]
set DMA1_Channel1_BASE [expr {$AHBPERIPH_BASE + 0x0008}]
set DMA1_Channel2_BASE [expr {$AHBPERIPH_BASE + 0x001C}]
set DMA1_Channel3_BASE [expr {$AHBPERIPH_BASE + 0x0030}]
set DMA1_Channel4_BASE [expr {$AHBPERIPH_BASE + 0x0044}]
set DMA1_Channel5_BASE [expr {$AHBPERIPH_BASE + 0x0058}]
set DMA1_Channel6_BASE [expr {$AHBPERIPH_BASE + 0x006C}]
set DMA1_Channel7_BASE [expr {$AHBPERIPH_BASE + 0x0080}]
set DMA2_BASE [expr {$AHBPERIPH_BASE + 0x0400}]
set DMA2_Channel1_BASE [expr {$AHBPERIPH_BASE + 0x0408}]
set DMA2_Channel2_BASE [expr {$AHBPERIPH_BASE + 0x041C}]
set DMA2_Channel3_BASE [expr {$AHBPERIPH_BASE + 0x0430}]
set DMA2_Channel4_BASE [expr {$AHBPERIPH_BASE + 0x0444}]
set DMA2_Channel5_BASE [expr {$AHBPERIPH_BASE + 0x0458}]
set RCC_BASE [expr {$AHBPERIPH_BASE + 0x1000}]
set CRC_BASE [expr {$AHBPERIPH_BASE + 0x3000}]
# /*Flash registers base address */
set FLASH_R_BASE [expr $AHBPERIPH_BASE + 0x2000]
set FLASH_R_BASE [expr {$AHBPERIPH_BASE + 0x2000}]
# /*Flash Option Bytes base address */
set OB_BASE 0x1FFFF800
# /*FSMC Bankx registers base address */
set FSMC_Bank1_R_BASE [expr $FSMC_R_BASE + 0x0000]
set FSMC_Bank1E_R_BASE [expr $FSMC_R_BASE + 0x0104]
set FSMC_Bank2_R_BASE [expr $FSMC_R_BASE + 0x0060]
set FSMC_Bank3_R_BASE [expr $FSMC_R_BASE + 0x0080]
set FSMC_Bank4_R_BASE [expr $FSMC_R_BASE + 0x00A0]
set FSMC_Bank1_R_BASE [expr {$FSMC_R_BASE + 0x0000}]
set FSMC_Bank1E_R_BASE [expr {$FSMC_R_BASE + 0x0104}]
set FSMC_Bank2_R_BASE [expr {$FSMC_R_BASE + 0x0060}]
set FSMC_Bank3_R_BASE [expr {$FSMC_R_BASE + 0x0080}]
set FSMC_Bank4_R_BASE [expr {$FSMC_R_BASE + 0x00A0}]
# /*Debug MCU registers base address */
set DBGMCU_BASE 0xE0042000
@@ -90,6 +90,6 @@ set DBGMCU_BASE 0xE0042000
# /*System Control Space memory map */
set SCS_BASE 0xE000E000
set SysTick_BASE [expr $SCS_BASE + 0x0010]
set NVIC_BASE [expr $SCS_BASE + 0x0100]
set SCB_BASE [expr $SCS_BASE + 0x0D00]
set SysTick_BASE [expr {$SCS_BASE + 0x0010}]
set NVIC_BASE [expr {$SCS_BASE + 0x0100}]
set SCB_BASE [expr {$SCS_BASE + 0x0D00}]