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tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change

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Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

In the TCL scripts distributed with OpenOCD there are 1700+ lines
that should be modified before switching to jimtcl 0.81.

Apply the script below on every script in tcl folder. It fixes
more than 92% of the lines

%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
 #!/usr/bin/perl -Wpi

 my $re_sym = qr{[a-z_][a-z0-9_]*}i;
 my $re_var = qr{(?:\$|\$::)$re_sym};
 my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i;
 my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)};
 my $re_op = qr{<<|>>|[+\-*/&|]};
 my $re_expr = qr{(
     (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item)
     \s*$re_op\s*
     (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\))
 )}x;

 # [expr [dict get $regsC100 SYM] + HEXNUM]
 s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/;

 # [ expr (EXPR) ]
 # [ expr EXPR ]
 # note: $re_expr captures '$3'
 s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/;
 s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/;
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---

Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6159
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo
2021-04-10 01:23:57 +02:00
parent 82b6a41117
commit f5657aa76e
61 changed files with 1592 additions and 1592 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
tcl/target/c100helper.tcl
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@@ -37,11 +37,11 @@ proc mr64bit {reg} {
# write a 64-bit register (memory mapped)
proc mw64bit {reg value} {
set high [expr $value >> 32]
set low [expr $value & 0xffffffff]
set high [expr {$value >> 32}]
set low [expr {$value & 0xffffffff}]
#echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low]
mww $reg $low
mww [expr $reg+4] $high
mww [expr {$reg+4}] $high
}
@@ -122,7 +122,7 @@ proc showAmbaClk {} {
set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
echo [format "PLL bypass bit: %d" $bypass]
if {$bypass == 1} {
echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
} else {
# nope, extract x,y,w and compute the PLL output freq.
set x [expr ($value(0) & 0x0001F0000) >> 16]
@@ -131,7 +131,7 @@ proc showAmbaClk {} {
echo [format "y: %d" $y]
set w [expr ($value(0) & 0x000000300) >> 8]
echo [format "w: %d" $w]
echo [format "Amba PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
}
}
@@ -154,7 +154,7 @@ proc setupAmbaClk {} {
set x [config x_amba]
set y [config y_amba]
echo [format "Setting Amba PLL to lock to %d MHz" [expr $CONFIG_SYS_HZ_CLOCK/1000000]]
echo [format "Setting Amba PLL to lock to %d MHz" [expr {$CONFIG_SYS_HZ_CLOCK/1000000}]]
#echo [format "setupAmbaClk: w= %d" $w]
#echo [format "setupAmbaClk: x= %d" $x]
#echo [format "setupAmbaClk: y= %d" $y]
@@ -174,7 +174,7 @@ proc setupAmbaClk {} {
sleep 1
# set X, W and X
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
# wait for PLL to lock
echo "Waiting for Amba PLL to lock"
while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
@@ -197,7 +197,7 @@ proc showArmClk {} {
set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
echo [format "PLL bypass bit: %d" $bypass]
if {$bypass == 1} {
echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
} else {
# nope, extract x,y,w and compute the PLL output freq.
set x [expr ($value(0) & 0x0001F0000) >> 16]
@@ -206,7 +206,7 @@ proc showArmClk {} {
echo [format "y: %d" $y]
set w [expr ($value(0) & 0x000000300) >> 8]
echo [format "w: %d" $w]
echo [format "Arm PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
}
}
@@ -228,7 +228,7 @@ proc setupArmClk {} {
set x [config x_arm]
set y [config y_arm]
echo [format "Setting Arm PLL to lock to %d MHz" [expr $CFG_ARM_CLOCK/1000000]]
echo [format "Setting Arm PLL to lock to %d MHz" [expr {$CFG_ARM_CLOCK/1000000}]]
#echo [format "setupArmClk: w= %d" $w]
#echo [format "setupArmaClk: x= %d" $x]
#echo [format "setupArmaClk: y= %d" $y]
@@ -248,7 +248,7 @@ proc setupArmClk {} {
sleep 1
# set X, W and X
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
# wait for PLL to lock
echo "Waiting for Amba PLL to lock"
while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
@@ -281,11 +281,11 @@ proc setupDDR2 {} {
# and not reset.
mmw $BLOCK_RESET_REG 0x0 $DDR_RST
set M [expr 1024 * 1024]
set DDR_SZ_1024M [expr 1024 * $M]
set DDR_SZ_256M [expr 256 * $M]
set DDR_SZ_128M [expr 128 * $M]
set DDR_SZ_64M [expr 64 * $M]
set M [expr {1024 * 1024}]
set DDR_SZ_1024M [expr {1024 * $M}]
set DDR_SZ_256M [expr {256 * $M}]
set DDR_SZ_128M [expr {128 * $M}]
set DDR_SZ_64M [expr {64 * $M}]
# ooma_board_detect returns DDR2 memory size
set tmp [ooma_board_detect]
if {$tmp == "128M"} {
@@ -299,7 +299,7 @@ proc setupDDR2 {} {
}
# Memory setup register
mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]
mww $MEMORY_MAX_ADDR [expr {($ddr_size - 1) + $MEMORY_BASE_ADDR}]
# disable ROM remap
mww $MEMORY_CR 0x0
# Take DDR controller out of reset
@@ -445,9 +445,9 @@ proc initC100 {} {
mww [expr $APB_ACCESS_WS_REG] 0x40
# AHB init
# // enable all 6 masters for ARAM
mmw $ASA_ARAM_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0
# // enable all 6 masters for EBUS
mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
mmw $ASA_EBUS_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0
# ARAM init
# // disable pipeline mode in ARAM