tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.
In the TCL scripts distributed with OpenOCD there are 1700+ lines
that should be modified before switching to jimtcl 0.81.
Apply the script below on every script in tcl folder. It fixes
more than 92% of the lines
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
#!/usr/bin/perl -Wpi
my $re_sym = qr{[a-z_][a-z0-9_]*}i;
my $re_var = qr{(?:\$|\$::)$re_sym};
my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i;
my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)};
my $re_op = qr{<<|>>|[+\-*/&|]};
my $re_expr = qr{(
(?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item)
\s*$re_op\s*
(?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\))
)}x;
# [expr [dict get $regsC100 SYM] + HEXNUM]
s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/;
# [ expr (EXPR) ]
# [ expr EXPR ]
# note: $re_expr captures '$3'
s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/;
s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/;
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6159
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo
@@ -22,53 +22,53 @@ source [find mem_helper.tcl]
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# PLL version 0x02: tested on dm355
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# REVISIT: On dm6446/dm357 the PLLRST polarity is different.
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proc pll_v02_setup {pll_addr mult config} {
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set pll_ctrl_addr [expr $pll_addr + 0x100]
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set pll_ctrl_addr [expr {$pll_addr + 0x100}]
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set pll_ctrl [mrw $pll_ctrl_addr]
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# 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
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# NOTE: this assumes we should clear that bit
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set pll_ctrl [expr $pll_ctrl & ~0x0100]
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set pll_ctrl [expr {$pll_ctrl & ~0x0100}]
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mww $pll_ctrl_addr $pll_ctrl
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# 2 - clear PLLENSRC (bit 5)
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set pll_ctrl [expr $pll_ctrl & ~0x0020]
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set pll_ctrl [expr {$pll_ctrl & ~0x0020}]
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mww $pll_ctrl_addr $pll_ctrl
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# 3 - clear PLLEN (bit 0) ... enter bypass mode
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set pll_ctrl [expr $pll_ctrl & ~0x0001]
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set pll_ctrl [expr {$pll_ctrl & ~0x0001}]
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mww $pll_ctrl_addr $pll_ctrl
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# 4 - wait at least 4 refclk cycles
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sleep 1
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# 5 - set PLLRST (bit 3)
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set pll_ctrl [expr $pll_ctrl | 0x0008]
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set pll_ctrl [expr {$pll_ctrl | 0x0008}]
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mww $pll_ctrl_addr $pll_ctrl
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# 6 - set PLLDIS (bit 4)
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set pll_ctrl [expr $pll_ctrl | 0x0010]
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set pll_ctrl [expr {$pll_ctrl | 0x0010}]
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mww $pll_ctrl_addr $pll_ctrl
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# 7 - clear PLLPWRDN (bit 1)
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set pll_ctrl [expr $pll_ctrl & ~0x0002]
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set pll_ctrl [expr {$pll_ctrl & ~0x0002}]
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mww $pll_ctrl_addr $pll_ctrl
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# 8 - clear PLLDIS (bit 4)
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set pll_ctrl [expr $pll_ctrl & ~0x0010]
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set pll_ctrl [expr {$pll_ctrl & ~0x0010}]
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mww $pll_ctrl_addr $pll_ctrl
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# 9 - optional: write prediv, postdiv, and pllm
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# NOTE: for dm355 PLL1, postdiv is controlled via MISC register
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mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff]
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mww [expr {$pll_addr + 0x0110}] [expr {($mult - 1) & 0xff}]
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if { [dict exists $config prediv] } {
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set div [dict get $config prediv]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0114] $div
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0114}] $div
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}
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if { [dict exists $config postdiv] } {
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set div [dict get $config postdiv]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0128] $div
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0128}] $div
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}
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# 10 - optional: set plldiv1, plldiv2, ...
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@@ -78,47 +78,47 @@ proc pll_v02_setup {pll_addr mult config} {
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set go 0
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if { [dict exists $config div1] } {
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set div [dict get $config div1]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0118] $div
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0118}] $div
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set go 1
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}
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if { [dict exists $config div2] } {
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set div [dict get $config div2]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x011c] $div
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x011c}] $div
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set go 1
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}
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if { [dict exists $config div3] } {
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set div [dict get $config div3]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0120] $div
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0120}] $div
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set go 1
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}
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if { [dict exists $config div4] } {
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set div [dict get $config div4]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0160] $div
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0160}] $div
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set go 1
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}
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if { [dict exists $config div5] } {
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set div [dict get $config div5]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0164] $div
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0164}] $div
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set go 1
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}
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if {$go != 0} {
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# write pllcmd.GO; poll pllstat.GO
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mww [expr $pll_addr + 0x0138] 0x01
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set pllstat [expr $pll_addr + 0x013c]
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mww [expr {$pll_addr + 0x0138}] 0x01
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set pllstat [expr {$pll_addr + 0x013c}]
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while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
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}
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mww [expr $pll_addr + 0x0138] 0x00
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mww [expr {$pll_addr + 0x0138}] 0x00
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# 11 - wait at least 5 usec for reset to finish
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# (assume covered by overheads including JTAG messaging)
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# 12 - clear PLLRST (bit 3)
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set pll_ctrl [expr $pll_ctrl & ~0x0008]
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set pll_ctrl [expr {$pll_ctrl & ~0x0008}]
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mww $pll_ctrl_addr $pll_ctrl
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# 13 - wait at least 8000 refclk cycles for PLL to lock
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@@ -126,53 +126,53 @@ proc pll_v02_setup {pll_addr mult config} {
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sleep 3
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# 14 - set PLLEN (bit 0) ... leave bypass mode
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set pll_ctrl [expr $pll_ctrl | 0x0001]
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set pll_ctrl [expr {$pll_ctrl | 0x0001}]
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mww $pll_ctrl_addr $pll_ctrl
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}
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# PLL version 0x03: tested on dm365
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proc pll_v03_setup {pll_addr mult config} {
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set pll_ctrl_addr [expr $pll_addr + 0x100]
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set pll_secctrl_addr [expr $pll_addr + 0x108]
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set pll_ctrl_addr [expr {$pll_addr + 0x100}]
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set pll_secctrl_addr [expr {$pll_addr + 0x108}]
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set pll_ctrl [mrw $pll_ctrl_addr]
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# 1 - power up the PLL
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set pll_ctrl [expr $pll_ctrl & ~0x0002]
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set pll_ctrl [expr {$pll_ctrl & ~0x0002}]
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mww $pll_ctrl_addr $pll_ctrl
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# 2 - clear PLLENSRC (bit 5)
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set pll_ctrl [expr $pll_ctrl & ~0x0020]
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set pll_ctrl [expr {$pll_ctrl & ~0x0020}]
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mww $pll_ctrl_addr $pll_ctrl
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# 2 - clear PLLEN (bit 0) ... enter bypass mode
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set pll_ctrl [expr $pll_ctrl & ~0x0001]
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set pll_ctrl [expr {$pll_ctrl & ~0x0001}]
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mww $pll_ctrl_addr $pll_ctrl
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# 3 - wait at least 4 refclk cycles
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sleep 1
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# 4 - set PLLRST (bit 3)
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set pll_ctrl [expr $pll_ctrl | 0x0008]
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set pll_ctrl [expr {$pll_ctrl | 0x0008}]
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mww $pll_ctrl_addr $pll_ctrl
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# 5 - wait at least 5 usec
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sleep 1
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# 6 - clear PLLRST (bit 3)
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set pll_ctrl [expr $pll_ctrl & ~0x0008]
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set pll_ctrl [expr {$pll_ctrl & ~0x0008}]
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mww $pll_ctrl_addr $pll_ctrl
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# 9 - optional: write prediv, postdiv, and pllm
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mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff]
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mww [expr {$pll_addr + 0x0110}] [expr {($mult / 2) & 0x1ff}]
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if { [dict exists $config prediv] } {
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set div [dict get $config prediv]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0114] $div
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0114}] $div
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}
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if { [dict exists $config postdiv] } {
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set div [dict get $config postdiv]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0128] $div
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0128}] $div
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}
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# 10 - write start sequence to PLLSECCTL
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@@ -187,99 +187,99 @@ proc pll_v03_setup {pll_addr mult config} {
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set aln 0
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if { [dict exists $config div1] } {
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set div [dict get $config div1]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0118] $div
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set aln [expr $aln | 0x1]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0118}] $div
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set aln [expr {$aln | 0x1}]
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} else {
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mww [expr $pll_addr + 0x0118] 0
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mww [expr {$pll_addr + 0x0118}] 0
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}
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if { [dict exists $config div2] } {
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set div [dict get $config div2]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x011c] $div
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set aln [expr $aln | 0x2]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x011c}] $div
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set aln [expr {$aln | 0x2}]
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} else {
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mww [expr $pll_addr + 0x011c] 0
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mww [expr {$pll_addr + 0x011c}] 0
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}
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if { [dict exists $config div3] } {
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set div [dict get $config div3]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0120] $div
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set aln [expr $aln | 0x4]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0120}] $div
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set aln [expr {$aln | 0x4}]
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} else {
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mww [expr $pll_addr + 0x0120] 0
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mww [expr {$pll_addr + 0x0120}] 0
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}
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if { [dict exists $config oscdiv] } {
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set div [dict get $config oscdiv]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0124] $div
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0124}] $div
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} else {
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mww [expr $pll_addr + 0x0124] 0
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mww [expr {$pll_addr + 0x0124}] 0
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}
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if { [dict exists $config div4] } {
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set div [dict get $config div4]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0160] $div
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set aln [expr $aln | 0x8]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0160}] $div
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set aln [expr {$aln | 0x8}]
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} else {
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mww [expr $pll_addr + 0x0160] 0
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mww [expr {$pll_addr + 0x0160}] 0
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}
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if { [dict exists $config div5] } {
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set div [dict get $config div5]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0164] $div
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set aln [expr $aln | 0x10]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0164}] $div
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set aln [expr {$aln | 0x10}]
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} else {
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mww [expr $pll_addr + 0x0164] 0
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mww [expr {$pll_addr + 0x0164}] 0
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}
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if { [dict exists $config div6] } {
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set div [dict get $config div6]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0168] $div
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set aln [expr $aln | 0x20]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0168}] $div
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set aln [expr {$aln | 0x20}]
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} else {
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mww [expr $pll_addr + 0x0168] 0
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mww [expr {$pll_addr + 0x0168}] 0
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}
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if { [dict exists $config div7] } {
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set div [dict get $config div7]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x016c] $div
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set aln [expr $aln | 0x40]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x016c}] $div
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set aln [expr {$aln | 0x40}]
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} else {
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mww [expr $pll_addr + 0x016c] 0
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mww [expr {$pll_addr + 0x016c}] 0
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}
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if { [dict exists $config div8] } {
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set div [dict get $config div8]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0170] $div
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set aln [expr $aln | 0x80]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0170}] $div
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set aln [expr {$aln | 0x80}]
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} else {
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mww [expr $pll_addr + 0x0170] 0
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mww [expr {$pll_addr + 0x0170}] 0
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}
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if { [dict exists $config div9] } {
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set div [dict get $config div9]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0174] $div
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set aln [expr $aln | 0x100]
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set div [expr {0x8000 | ($div - 1)}]
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mww [expr {$pll_addr + 0x0174}] $div
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set aln [expr {$aln | 0x100}]
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} else {
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mww [expr $pll_addr + 0x0174] 0
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mww [expr {$pll_addr + 0x0174}] 0
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}
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if {$aln != 0} {
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# clear pllcmd.GO
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mww [expr $pll_addr + 0x0138] 0x00
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mww [expr {$pll_addr + 0x0138}] 0x00
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# write alingment flags
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mww [expr $pll_addr + 0x0140] $aln
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mww [expr {$pll_addr + 0x0140}] $aln
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# write pllcmd.GO; poll pllstat.GO
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mww [expr $pll_addr + 0x0138] 0x01
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set pllstat [expr $pll_addr + 0x013c]
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mww [expr {$pll_addr + 0x0138}] 0x01
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set pllstat [expr {$pll_addr + 0x013c}]
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while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
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}
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mww [expr $pll_addr + 0x0138] 0x00
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mww [expr {$pll_addr + 0x0138}] 0x00
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set addr [dict get $config ctladdr]
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while {[expr [mrw $addr] & 0x0e000000] != 0x0e000000} { sleep 1 }
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# 12 - set PLLEN (bit 0) ... leave bypass mode
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set pll_ctrl [expr $pll_ctrl | 0x0001]
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set pll_ctrl [expr {$pll_ctrl | 0x0001}]
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mww $pll_ctrl_addr $pll_ctrl
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}
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@@ -290,26 +290,26 @@ proc pll_v03_setup {pll_addr mult config} {
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proc psc_enable {module} {
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set psc_addr 0x01c41000
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# write MDCTL
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mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
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mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x03 0x1f
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}
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# prepare a non-DSP module to be reset; finish with psc_go
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proc psc_reset {module} {
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set psc_addr 0x01c41000
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# write MDCTL
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mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f
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mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x01 0x1f
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}
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||||
# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
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proc psc_go {} {
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set psc_addr 0x01c41000
|
||||
set ptstat_addr [expr $psc_addr + 0x0128]
|
||||
set ptstat_addr [expr {$psc_addr + 0x0128}]
|
||||
|
||||
# just in case PTSTAT.go isn't clear
|
||||
while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
|
||||
|
||||
# write PTCMD.go ... ignoring any DSP power domain
|
||||
mww [expr $psc_addr + 0x0120] 1
|
||||
mww [expr {$psc_addr + 0x0120}] 1
|
||||
|
||||
# wait for PTSTAT.go to clear (again ignoring DSP power domain)
|
||||
while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
|
||||
@@ -344,34 +344,34 @@ proc davinci_wdog_reset {} {
|
||||
#
|
||||
|
||||
# EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
|
||||
mww phys [expr $timer2_phys + 0x28] 0x00004000
|
||||
mww phys [expr {$timer2_phys + 0x28}] 0x00004000
|
||||
|
||||
#
|
||||
# Part II -- in case watchdog hasn't been set up
|
||||
#
|
||||
|
||||
# TCR: disable, force internal clock source
|
||||
mww phys [expr $timer2_phys + 0x20] 0
|
||||
mww phys [expr {$timer2_phys + 0x20}] 0
|
||||
|
||||
# TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
|
||||
mww phys [expr $timer2_phys + 0x24] 0
|
||||
mww phys [expr $timer2_phys + 0x24] 0x110b
|
||||
mww phys [expr {$timer2_phys + 0x24}] 0
|
||||
mww phys [expr {$timer2_phys + 0x24}] 0x110b
|
||||
|
||||
# clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
|
||||
# so watchdog triggers ASAP
|
||||
mww phys [expr $timer2_phys + 0x10] 0
|
||||
mww phys [expr $timer2_phys + 0x14] 0
|
||||
mww phys [expr $timer2_phys + 0x18] 0
|
||||
mww phys [expr $timer2_phys + 0x1c] 0
|
||||
mww phys [expr {$timer2_phys + 0x10}] 0
|
||||
mww phys [expr {$timer2_phys + 0x14}] 0
|
||||
mww phys [expr {$timer2_phys + 0x18}] 0
|
||||
mww phys [expr {$timer2_phys + 0x1c}] 0
|
||||
|
||||
# WDTCR: put into pre-active state, then active
|
||||
mww phys [expr $timer2_phys + 0x28] 0xa5c64000
|
||||
mww phys [expr $timer2_phys + 0x28] 0xda7e4000
|
||||
mww phys [expr {$timer2_phys + 0x28}] 0xa5c64000
|
||||
mww phys [expr {$timer2_phys + 0x28}] 0xda7e4000
|
||||
|
||||
#
|
||||
# Part III -- it's ready to rumble
|
||||
#
|
||||
|
||||
# WDTCR: write invalid WDKEY to trigger reset
|
||||
mww phys [expr $timer2_phys + 0x28] 0x00004000
|
||||
mww phys [expr {$timer2_phys + 0x28}] 0x00004000
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user