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RTOS support: Add FPU support for FreeRTOS

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Add new structure for for working with FPU thread in thread view.
This modification support both stacking.
When FPU is activated, LR must be validated to check if the FPU
register are push on the stack. This is mandatory to find the correct
stack pointer position.

the modified code was inspired and adapted from

88d2003bb8

Change-Id: I6641926aa14e7216cacb399cbc8bb0db324cc9fc
Signed-off-by: Jonathan Dumaresq <jdumaresq@cimeq.qc.ca>
Reviewed-on: http://openocd.zylin.com/3397
Tested-by: jenkins
Reviewed-by: Sergey A. Borshch <sb-sf@users.sourceforge.net>
Reviewed-by: Harry Zhurov <harry.zhurov@gmail.com>
Reviewed-by: Anton Gusev
Reviewed-by: Михаил Цивинский <mtsivinsky@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This commit is contained in:
Jonathan Dumaresq
2016-04-06 16:00:06 -04:00
committed by Freddie Chopin
parent 5396ec5dcc
commit f5b7033742
3 changed files with 111 additions and 2 deletions
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57
src/rtos/rtos_standard_stackings.c
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@@ -45,6 +45,47 @@ static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[
{ 0x3c, 32 }, /* xPSR */
};
static const struct stack_register_offset rtos_standard_Cortex_M4F_stack_offsets[] = {
{ 0x24, 32 }, /* r0 */
{ 0x28, 32 }, /* r1 */
{ 0x2c, 32 }, /* r2 */
{ 0x30, 32 }, /* r3 */
{ 0x00, 32 }, /* r4 */
{ 0x04, 32 }, /* r5 */
{ 0x08, 32 }, /* r6 */
{ 0x0c, 32 }, /* r7 */
{ 0x10, 32 }, /* r8 */
{ 0x14, 32 }, /* r9 */
{ 0x18, 32 }, /* r10 */
{ 0x1c, 32 }, /* r11 */
{ 0x34, 32 }, /* r12 */
{ -2, 32 }, /* sp */
{ 0x38, 32 }, /* lr */
{ 0x3c, 32 }, /* pc */
{ 0x40, 32 }, /* xPSR */
};
static const struct stack_register_offset rtos_standard_Cortex_M4F_FPU_stack_offsets[] = {
{ 0x64, 32 }, /* r0 */
{ 0x68, 32 }, /* r1 */
{ 0x6c, 32 }, /* r2 */
{ 0x70, 32 }, /* r3 */
{ 0x00, 32 }, /* r4 */
{ 0x04, 32 }, /* r5 */
{ 0x08, 32 }, /* r6 */
{ 0x0c, 32 }, /* r7 */
{ 0x10, 32 }, /* r8 */
{ 0x14, 32 }, /* r9 */
{ 0x18, 32 }, /* r10 */
{ 0x1c, 32 }, /* r11 */
{ 0x74, 32 }, /* r12 */
{ -2, 32 }, /* sp */
{ 0x78, 32 }, /* lr */
{ 0x7c, 32 }, /* pc */
{ 0x80, 32 }, /* xPSR */
};
static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[] = {
{ 0x08, 32 }, /* r0 (a1) */
{ 0x0c, 32 }, /* r1 (a2) */
@@ -198,6 +239,22 @@ const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
rtos_standard_Cortex_M3_stack_offsets /* register_offsets */
};
const struct rtos_register_stacking rtos_standard_Cortex_M4F_stacking = {
0x44, /* stack_registers_size 4 more for LR*/
-1, /* stack_growth_direction */
ARMV7M_NUM_CORE_REGS, /* num_output_registers */
rtos_standard_Cortex_M3_stack_align, /* stack_alignment */
rtos_standard_Cortex_M4F_stack_offsets /* register_offsets */
};
const struct rtos_register_stacking rtos_standard_Cortex_M4F_FPU_stacking = {
0xcc, /* stack_registers_size 4 more for LR + 48 more for FPU S0-S15 register*/
-1, /* stack_growth_direction */
ARMV7M_NUM_CORE_REGS, /* num_output_registers */
rtos_standard_Cortex_M3_stack_align, /* stack_alignment */
rtos_standard_Cortex_M4F_FPU_stack_offsets /* register_offsets */
};
const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking = {
0x48, /* stack_registers_size */
-1, /* stack_growth_direction */