Cadence virtual debug interface (vdebug) integration

Change-Id: I1bc105b3addc3f34161c2356c482ff3011e3f2cc
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6097
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

tcl/target/vd_riscv.cfg

@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# RISCV core
+
+if {![info exists _HARTID]} {
+	set _HARTID 0x00
+}
+if {![info exists _CHIPNAME]} {
+	set _CHIPNAME riscv
+}
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid $_HARTID
+
+riscv set_reset_timeout_sec 120
+riscv set_command_timeout_sec 120
+# prefer to use sba for system bus access
+riscv set_prefer_sba on