From ff550ed0b0c6f4e15cbd97a5248cb33ca5d21c88 Mon Sep 17 00:00:00 2001 From: Henrik Mau Date: Tue, 25 Feb 2025 15:54:44 +0000 Subject: [PATCH] flash/nor/max32xxx: Fix failing flash step for internal flash When attempting to write to internal flash the flashing step fails with 'Error: timeout waiting for algorithm, a target reset is recommended'. Updated flashing algorithm for MAX32xxx to fix this. Change-Id: I51350c1320c9699ddcf6cb28d9299538bece4c4f Signed-off-by: Henrik Mau Reviewed-on: https://review.openocd.org/c/openocd/+/8794 Tested-by: jenkins Reviewed-by: Antonio Borneo Reviewed-by: zapb --- contrib/loaders/flash/max32xxx/Makefile | 25 +- contrib/loaders/flash/max32xxx/algo_options.h | 14 + contrib/loaders/flash/max32xxx/flc_regs.h | 238 ++++++ contrib/loaders/flash/max32xxx/gcr_regs.h | 777 ++++++++++++++++++ contrib/loaders/flash/max32xxx/max32xxx.inc | 6 - contrib/loaders/flash/max32xxx/max32xxx.s | 59 -- .../loaders/flash/max32xxx/max32xxx_write.c | 282 +++++++ .../flash/max32xxx/max32xxx_write_arm.inc | 57 ++ contrib/loaders/flash/max32xxx/tpu_regs.h | 572 +++++++++++++ src/flash/nor/max32xxx.c | 711 +++++++++------- 10 files changed, 2355 insertions(+), 386 deletions(-) create mode 100644 contrib/loaders/flash/max32xxx/algo_options.h create mode 100644 contrib/loaders/flash/max32xxx/flc_regs.h create mode 100644 contrib/loaders/flash/max32xxx/gcr_regs.h delete mode 100644 contrib/loaders/flash/max32xxx/max32xxx.inc delete mode 100644 contrib/loaders/flash/max32xxx/max32xxx.s create mode 100644 contrib/loaders/flash/max32xxx/max32xxx_write.c create mode 100644 contrib/loaders/flash/max32xxx/max32xxx_write_arm.inc create mode 100644 contrib/loaders/flash/max32xxx/tpu_regs.h diff --git a/contrib/loaders/flash/max32xxx/Makefile b/contrib/loaders/flash/max32xxx/Makefile index 1565c811c..fe7666f84 100644 --- a/contrib/loaders/flash/max32xxx/Makefile +++ b/contrib/loaders/flash/max32xxx/Makefile @@ -1,21 +1,30 @@ # SPDX-License-Identifier: GPL-2.0-or-later +TARGET=max32xxx_write +ENTRY=algo_write + BIN2C = ../../../../src/helper/bin2char.sh -CROSS_COMPILE ?= arm-none-eabi- -AS = $(CROSS_COMPILE)as -OBJCOPY = $(CROSS_COMPILE)objcopy +PREFIX=arm-none-eabi +CFLAGS=-mthumb -mcpu=cortex-m4 -Wa,-mimplicit-it=thumb -all: max32xxx.inc +all: $(TARGET).inc -%.elf: %.s - $(AS) $< -o $@ +%.o: %.c + $(PREFIX)-gcc $(CFLAGS) -Os -Wall -c ${<} -o ${@} + +%.elf: %.o + $(PREFIX)-ld -nostdlib --entry $(ENTRY) ${<} -o ${@} + $(PREFIX)-size ${@} %.bin: %.elf - $(OBJCOPY) -Obinary $< $@ + $(PREFIX)-objcopy -O binary ${<} ${@} %.inc: %.bin $(BIN2C) < $< > $@ +%.dasm: %.o + $(PREFIX)-objdump -S ${<} > ${TARGET}.dasm + clean: - -rm -f *.elf *.bin *.inc + rm -rf $(TARGET).bin $(TARGET).elf $(TARGET).o $(TARGET).dasm $(TARGET).inc diff --git a/contrib/loaders/flash/max32xxx/algo_options.h b/contrib/loaders/flash/max32xxx/algo_options.h new file mode 100644 index 000000000..a4902e08a --- /dev/null +++ b/contrib/loaders/flash/max32xxx/algo_options.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (C) 2016 by Maxim Integrated * + * Copyright (C) 2025 Analog Devices, Inc. * + ***************************************************************************/ + +#define OPTIONS_128 0x01 /* Perform 128 bit flash writes */ +#define OPTIONS_ENC 0x02 /* Encrypt the flash contents */ +#define OPTIONS_AUTH 0x04 /* Authenticate the flash contents */ +#define OPTIONS_COUNT 0x08 /* Add counter values to authentication */ +#define OPTIONS_INTER 0x10 /* Interleave the authentication and count values*/ +#define OPTIONS_RELATIVE_XOR 0x20 /* Only XOR the offset of the address when encrypting */ +#define OPTIONS_KEYSIZE 0x40 /* Use a 256 bit KEY */ diff --git a/contrib/loaders/flash/max32xxx/flc_regs.h b/contrib/loaders/flash/max32xxx/flc_regs.h new file mode 100644 index 000000000..9179589dd --- /dev/null +++ b/contrib/loaders/flash/max32xxx/flc_regs.h @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (C) 2016 by Maxim Integrated * + * Copyright (C) 2025 Analog Devices, Inc. * + ***************************************************************************/ + +#ifndef _FLC_REGS_H_ +#define _FLC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__ICCARM__) +#pragma system_include +#endif + +/*/ @cond */ +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/*/ @endcond */ + +/* **** Definitions **** */ + +/** + * @ingroup flc + * @defgroup flc_registers Registers + * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + * @description Flash Memory Control. + */ + +/** + * @ingroup flc_registers + * Structure type to access the FLC Registers. + */ +struct mxc_flc_regs { + __IO uint32_t addr; /**< \b 0x00:<\tt> FLC ADDR Register */ + __IO uint32_t clkdiv; /**< \b 0x04:<\tt> FLC CLKDIV Register */ + __IO uint32_t cn; /**< \b 0x08:<\tt> FLC CN Register */ + __R uint32_t rsv_0xc_0x23[6]; + __IO uint32_t intr; /**< \b 0x024:<\tt> FLC INTR Register */ + __R uint32_t rsv_0x28_0x2f[2]; + __IO uint32_t data[4]; /**< \b 0x30:<\tt> FLC DATA Register */ + __O uint32_t acntl; /**< \b 0x40:<\tt> FLC ACNTL Register */ +}; + +/* Register offsets for module FLC */ +/** + * @ingroup flc_registers + * @defgroup FLC_Register_Offsets Register Offsets + * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. + * @{ + */ +#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: 0x0x000 */ +#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: 0x0x004 */ +#define MXC_R_FLC_CN ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: 0x0x008 */ +#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: 0x0x024 */ +#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: 0x0x030 */ +#define MXC_R_FLC_ACNTL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: 0x0x040 */ +/**@} end of group flc_registers */ + +/** + * @ingroup flc_registers + * @defgroup ADDR_Register + * @brief Flash Write Address. + * @{ + */ +#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ +#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ + +/**@} end of group ADDR_Register */ + +/** + * @ingroup flc_registers + * @defgroup CLKDIV_Register + * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 + * MHz clock for Flash controller. + * @{ + */ +#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ +#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ + +/**@} end of group CLKDIV_Register */ + +/** + * @ingroup flc_registers + * @defgroup CN_Register + * @brief Flash Control Register. + * @{ + */ +#define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */ +#define MXC_F_FLC_CN_WR ((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */ +#define MXC_V_FLC_CN_WR_COMPLETE ((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value */ +#define MXC_S_FLC_CN_WR_COMPLETE (MXC_V_FLC_CN_WR_COMPLETE << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE Setting */ +#define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL) /**< CN_WR_START Value */ +#define MXC_S_FLC_CN_WR_START (MXC_V_FLC_CN_WR_START << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START Setting */ + +#define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */ +#define MXC_F_FLC_CN_ME ((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */ + +#define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */ +#define MXC_F_FLC_CN_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */ + +#define MXC_F_FLC_CN_WDTH_POS 4 /**< CN_WDTH Position */ +#define MXC_F_FLC_CN_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */ +#define MXC_V_FLC_CN_WDTH_SIZE128 ((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */ +#define MXC_S_FLC_CN_WDTH_SIZE128 (MXC_V_FLC_CN_WDTH_SIZE128 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */ +#define MXC_V_FLC_CN_WDTH_SIZE32 ((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value */ +#define MXC_S_FLC_CN_WDTH_SIZE32 (MXC_V_FLC_CN_WDTH_SIZE32 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE32 Setting */ + +#define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */ +#define MXC_F_FLC_CN_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */ +#define MXC_V_FLC_CN_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */ +#define MXC_S_FLC_CN_ERASE_CODE_NOP \ + (MXC_V_FLC_CN_ERASE_CODE_NOP << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */ +#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */ +#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE \ + (MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting */ +#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */ +#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL \ + (MXC_V_FLC_CN_ERASE_CODE_ERASEALL << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting */ + +#define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */ +#define MXC_F_FLC_CN_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */ +#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL) /**< CN_PEND_IDLE Value */ +#define MXC_S_FLC_CN_PEND_IDLE (MXC_V_FLC_CN_PEND_IDLE << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE Setting */ +#define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL) /**< CN_PEND_BUSY Value */ +#define MXC_S_FLC_CN_PEND_BUSY (MXC_V_FLC_CN_PEND_BUSY << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */ + +#define MXC_F_FLC_CN_LVE_POS 25 /**< CN_LVE Position */ +#define MXC_F_FLC_CN_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */ +#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL) /**< CN_LVE_DIS Value */ +#define MXC_S_FLC_CN_LVE_DIS (MXC_V_FLC_CN_LVE_DIS << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting */ +#define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL) /**< CN_LVE_EN Value */ +#define MXC_S_FLC_CN_LVE_EN (MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting */ + +#define MXC_F_FLC_CN_BRST_POS 27 /**< CN_BRST Position */ +#define MXC_F_FLC_CN_BRST ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */ +#define MXC_V_FLC_CN_BRST_DISABLE ((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */ +#define MXC_S_FLC_CN_BRST_DISABLE (MXC_V_FLC_CN_BRST_DISABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */ +#define MXC_V_FLC_CN_BRST_ENABLE ((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value */ +#define MXC_S_FLC_CN_BRST_ENABLE (MXC_V_FLC_CN_BRST_ENABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_ENABLE Setting */ + +#define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */ +#define MXC_F_FLC_CN_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */ +#define MXC_V_FLC_CN_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */ +#define MXC_S_FLC_CN_UNLOCK_UNLOCKED \ + (MXC_V_FLC_CN_UNLOCK_UNLOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */ +#define MXC_V_FLC_CN_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CN_UNLOCK_LOCKED Value */ +#define MXC_S_FLC_CN_UNLOCK_LOCKED \ + (MXC_V_FLC_CN_UNLOCK_LOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_LOCKED Setting */ + +/**@} end of group CN_Register */ + +/** + * @ingroup flc_registers + * @defgroup INTR_Register + * @brief Flash Interrupt Register. + * @{ + */ +#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ +#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ +#define MXC_V_FLC_INTR_DONE_INACTIVE ((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */ +#define MXC_S_FLC_INTR_DONE_INACTIVE \ + (MXC_V_FLC_INTR_DONE_INACTIVE << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */ +#define MXC_V_FLC_INTR_DONE_PENDING ((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */ +#define MXC_S_FLC_INTR_DONE_PENDING \ + (MXC_V_FLC_INTR_DONE_PENDING << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */ + +#define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */ +#define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */ +#define MXC_V_FLC_INTR_AF_NOERROR ((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */ +#define MXC_S_FLC_INTR_AF_NOERROR (MXC_V_FLC_INTR_AF_NOERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */ +#define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */ +#define MXC_S_FLC_INTR_AF_ERROR (MXC_V_FLC_INTR_AF_ERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR Setting */ + +#define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ +#define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ +#define MXC_V_FLC_INTR_DONEIE_DISABLE ((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */ +#define MXC_S_FLC_INTR_DONEIE_DISABLE \ + (MXC_V_FLC_INTR_DONEIE_DISABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */ +#define MXC_V_FLC_INTR_DONEIE_ENABLE ((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */ +#define MXC_S_FLC_INTR_DONEIE_ENABLE \ + (MXC_V_FLC_INTR_DONEIE_ENABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */ + +#define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ +#define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ + +/**@} end of group INTR_Register */ + +/** + * @ingroup flc_registers + * @defgroup DATA_Register + * @brief Flash Write Data. + * @{ + */ +#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ +#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ + +/**@} end of group DATA_Register */ + +/** + * @ingroup flc_registers + * @defgroup ACNTL_Register + * @brief Access Control Register. Writing the ACNTL register with the following values in + * the order shown, allows read and write access to the system and user Information + * block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = + * 0x9608b2c1. When unlocked, a write of any word will disable access to system and + * user information block. Readback of this register is always zero. + * @{ + */ +#define MXC_F_FLC_ACNTL_ACNTL_POS 0 /**< ACNTL_ACNTL Position */ +#define MXC_F_FLC_ACNTL_ACNTL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */ + +/**@} end of group ACNTL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _FLC_REGS_H_ */ diff --git a/contrib/loaders/flash/max32xxx/gcr_regs.h b/contrib/loaders/flash/max32xxx/gcr_regs.h new file mode 100644 index 000000000..0c5ccdbf3 --- /dev/null +++ b/contrib/loaders/flash/max32xxx/gcr_regs.h @@ -0,0 +1,777 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (C) 2016 by Maxim Integrated * + * Copyright (C) 2025 Analog Devices, Inc. * + ***************************************************************************/ + +#ifndef _GCR_REGS_H_ +#define _GCR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__ICCARM__) +#pragma system_include +#endif + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +/*/ @cond */ +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/*/ @endcond */ + +/* **** Definitions **** */ + +/** + * @ingroup gcr + * @defgroup gcr_registers GCR_Registers + * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. + * @details Global Control Registers. + */ + +/** + * @ingroup gcr_registers + * Structure type to access the GCR Registers. + */ +struct mxc_gcr_regs { + __IO uint32_t scon; /**< \b 0x00: GCR SCON Register */ + __IO uint32_t rstr0; /**< \b 0x04: GCR RSTR0 Register */ + __IO uint32_t clkcn; /**< \b 0x08: GCR CLKCN Register */ + __IO uint32_t pm; /**< \b 0x0C: GCR PM Register */ + __R uint32_t rsv_0x10_0x17[2]; + __IO uint32_t pckdiv; /**< \b 0x18: GCR PCKDIV Register */ + __R uint32_t rsv_0x1c_0x23[2]; + __IO uint32_t perckcn0; /**< \b 0x24: GCR PERCKCN0 Register */ + __IO uint32_t memckcn; /**< \b 0x28: GCR MEMCKCN Register */ + __IO uint32_t memzcn; /**< \b 0x2C: GCR MEMZCN Register */ + __R uint32_t rsv_0x30_0x3f[4]; + __IO uint32_t sysst; /**< \b 0x40: GCR SYSST Register */ + __IO uint32_t rstr1; /**< \b 0x44: GCR RSTR1 Register */ + __IO uint32_t perckcn1; /**< \b 0x48: GCR PERCKCN1 Register */ + __IO uint32_t evten; /**< \b 0x4C: GCR EVTEN Register */ + __I uint32_t revision; /**< \b 0x50: GCR REVISION Register */ + __IO uint32_t syssie; /**< \b 0x54: GCR SYSSIE Register */ + __R uint32_t rsv_0x58_0x63[3]; + __IO uint32_t eccerr; /**< \b 0x64: GCR ECCERR Register */ + __IO uint32_t eccnded; /**< \b 0x68: GCR ECCNDED Register */ + __IO uint32_t eccirqen; /**< \b 0x6C: GCR ECCIRQEN Register */ + __IO uint32_t eccerrad; /**< \b 0x70: GCR ECCERRAD Register */ +}; + +/* Register offsets for module GCR */ +/** + * @ingroup gcr_registers + * @defgroup GCR_Register_Offsets Register Offsets + * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. + * @{ + */ +#define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: 0x0000 */ +#define MXC_R_GCR_RSTR0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: 0x0004 */ +#define MXC_R_GCR_CLKCN ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: 0x0008 */ +#define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: 0x000C */ +#define MXC_R_GCR_PCKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: 0x0018 */ +#define MXC_R_GCR_PERCKCN0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: 0x0024 */ +#define MXC_R_GCR_MEMCKCN ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: 0x0028 */ +#define MXC_R_GCR_MEMZCN ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: 0x002C */ +#define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: 0x0040 */ +#define MXC_R_GCR_RSTR1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: 0x0044 */ +#define MXC_R_GCR_PERCKCN1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: 0x0048 */ +#define MXC_R_GCR_EVTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: 0x004C */ +#define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */ +#define MXC_R_GCR_SYSSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: 0x0054 */ +#define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: 0x0064 */ +#define MXC_R_GCR_ECCNDED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: 0x0068 */ +#define MXC_R_GCR_ECCIRQEN ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: 0x006C */ +#define MXC_R_GCR_ECCERRAD ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: 0x0070 */ + /**@} end of group gcr_registers */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SCON GCR_SCON + * @brief System Control. + * @{ + */ +#define MXC_F_GCR_SCON_BSTAPEN_POS 0 /**< SCON_BSTAPEN Position */ +#define MXC_F_GCR_SCON_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SCON_BSTAPEN_POS)) /**< SCON_BSTAPEN Mask */ +#define MXC_V_GCR_SCON_BSTAPEN_DIS ((uint32_t)0x0UL) /**< SCON_BSTAPEN_DIS Value */ +#define MXC_S_GCR_SCON_BSTAPEN_DIS \ + (MXC_V_GCR_SCON_BSTAPEN_DIS << MXC_F_GCR_SCON_BSTAPEN_POS) /**< SCON_BSTAPEN_DIS Setting */ +#define MXC_V_GCR_SCON_BSTAPEN_EN ((uint32_t)0x1UL) /**< SCON_BSTAPEN_EN Value */ +#define MXC_S_GCR_SCON_BSTAPEN_EN \ + (MXC_V_GCR_SCON_BSTAPEN_EN << MXC_F_GCR_SCON_BSTAPEN_POS) /**< SCON_BSTAPEN_EN Setting */ + +#define MXC_F_GCR_SCON_SBUSARB_POS 1 /**< SCON_SBUSARB Position */ +#define MXC_F_GCR_SCON_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */ +#define MXC_V_GCR_SCON_SBUSARB_FIX ((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */ +#define MXC_S_GCR_SCON_SBUSARB_FIX \ + (MXC_V_GCR_SCON_SBUSARB_FIX << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */ +#define MXC_V_GCR_SCON_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */ +#define MXC_S_GCR_SCON_SBUSARB_ROUND \ + (MXC_V_GCR_SCON_SBUSARB_ROUND << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */ + +#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */ +#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP \ + ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */ +#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL ((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */ +#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL \ + (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL \ + << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_NORMAL Setting */ +#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED ((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */ +#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED \ + (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED \ + << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Setting */ + +#define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */ +#define MXC_F_GCR_SCON_CCACHE_FLUSH \ + ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH Mask */ +#define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL ((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */ +#define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL \ + (MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL Setting */ +#define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH ((uint32_t)0x1UL) /**< SCON_CCACHE_FLUSH_FLUSH Value */ +#define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH \ + (MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH Setting */ + +#define MXC_F_GCR_SCON_CCHK_POS 13 /**< SCON_CCHK Position */ +#define MXC_F_GCR_SCON_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCHK_POS)) /**< SCON_CCHK Mask */ +#define MXC_V_GCR_SCON_CCHK_COMPLETE ((uint32_t)0x0UL) /**< SCON_CCHK_COMPLETE Value */ +#define MXC_S_GCR_SCON_CCHK_COMPLETE \ + (MXC_V_GCR_SCON_CCHK_COMPLETE << MXC_F_GCR_SCON_CCHK_POS) /**< SCON_CCHK_COMPLETE Setting */ +#define MXC_V_GCR_SCON_CCHK_START ((uint32_t)0x1UL) /**< SCON_CCHK_START Value */ +#define MXC_S_GCR_SCON_CCHK_START (MXC_V_GCR_SCON_CCHK_START << MXC_F_GCR_SCON_CCHK_POS) /**< SCON_CCHK_START Setting \ + */ + +#define MXC_F_GCR_SCON_CHKRES_POS 15 /**< SCON_CHKRES Position */ +#define MXC_F_GCR_SCON_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CHKRES_POS)) /**< SCON_CHKRES Mask */ +#define MXC_V_GCR_SCON_CHKRES_PASS ((uint32_t)0x0UL) /**< SCON_CHKRES_PASS Value */ +#define MXC_S_GCR_SCON_CHKRES_PASS \ + (MXC_V_GCR_SCON_CHKRES_PASS << MXC_F_GCR_SCON_CHKRES_POS) /**< SCON_CHKRES_PASS Setting */ +#define MXC_V_GCR_SCON_CHKRES_FAIL ((uint32_t)0x1UL) /**< SCON_CHKRES_FAIL Value */ +#define MXC_S_GCR_SCON_CHKRES_FAIL \ + (MXC_V_GCR_SCON_CHKRES_FAIL << MXC_F_GCR_SCON_CHKRES_POS) /**< SCON_CHKRES_FAIL Setting */ + +#define MXC_F_GCR_SCON_OVR_POS 16 /**< SCON_OVR Position */ +#define MXC_F_GCR_SCON_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SCON_OVR_POS)) /**< SCON_OVR Mask */ +#define MXC_V_GCR_SCON_OVR_0_9V ((uint32_t)0x0UL) /**< SCON_OVR_0_9V Value */ +#define MXC_S_GCR_SCON_OVR_0_9V (MXC_V_GCR_SCON_OVR_0_9V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_0_9V Setting */ +#define MXC_V_GCR_SCON_OVR_1_0V ((uint32_t)0x1UL) /**< SCON_OVR_1_0V Value */ +#define MXC_S_GCR_SCON_OVR_1_0V (MXC_V_GCR_SCON_OVR_1_0V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_1_0V Setting */ +#define MXC_V_GCR_SCON_OVR_1_1V ((uint32_t)0x2UL) /**< SCON_OVR_1_1V Value */ +#define MXC_S_GCR_SCON_OVR_1_1V (MXC_V_GCR_SCON_OVR_1_1V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_1_1V Setting */ + +#define MXC_F_GCR_SCON_MEMPROT_EN_POS 20 /**< SCON_MEMPROT_EN Position */ +#define MXC_F_GCR_SCON_MEMPROT_EN ((uint32_t)(0x1UL << MXC_F_GCR_SCON_MEMPROT_EN_POS)) /**< SCON_MEMPROT_EN Mask */ +#define MXC_V_GCR_SCON_MEMPROT_EN_DIS ((uint32_t)0x0UL) /**< SCON_MEMPROT_EN_DIS Value */ +#define MXC_S_GCR_SCON_MEMPROT_EN_DIS \ + (MXC_V_GCR_SCON_MEMPROT_EN_DIS << MXC_F_GCR_SCON_MEMPROT_EN_POS) /**< SCON_MEMPROT_EN_DIS Setting */ +#define MXC_V_GCR_SCON_MEMPROT_EN_EN ((uint32_t)0x1UL) /**< SCON_MEMPROT_EN_EN Value */ +#define MXC_S_GCR_SCON_MEMPROT_EN_EN \ + (MXC_V_GCR_SCON_MEMPROT_EN_EN << MXC_F_GCR_SCON_MEMPROT_EN_POS) /**< SCON_MEMPROT_EN_EN Setting */ + +#define MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS 21 /**< SCON_MEMPROT_KEYSZ Position */ +#define MXC_F_GCR_SCON_MEMPROT_KEYSZ \ + ((uint32_t)(0x1UL << MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS)) /**< SCON_MEMPROT_KEYSZ Mask */ +#define MXC_V_GCR_SCON_MEMPROT_KEYSZ_128 ((uint32_t)0x0UL) /**< SCON_MEMPROT_KEYSZ_128 Value */ +#define MXC_S_GCR_SCON_MEMPROT_KEYSZ_128 \ + (MXC_V_GCR_SCON_MEMPROT_KEYSZ_128 << MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS) /**< SCON_MEMPROT_KEYSZ_128 Setting */ +#define MXC_V_GCR_SCON_MEMPROT_KEYSZ_256 ((uint32_t)0x1UL) /**< SCON_MEMPROT_KEYSZ_256 Value */ +#define MXC_S_GCR_SCON_MEMPROT_KEYSZ_256 \ + (MXC_V_GCR_SCON_MEMPROT_KEYSZ_256 << MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS) /**< SCON_MEMPROT_KEYSZ_256 Setting */ + +/**@} end of group GCR_SCON_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_RSTR0 GCR_RSTR0 + * @brief Reset. + * @{ + */ +#define MXC_F_GCR_RSTR0_DMA_POS 0 /**< RSTR0_DMA Position */ +#define MXC_F_GCR_RSTR0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */ +#define MXC_V_GCR_RSTR0_DMA_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_DMA_RESET_DONE Value */ +#define MXC_S_GCR_RSTR0_DMA_RESET_DONE \ + (MXC_V_GCR_RSTR0_DMA_RESET_DONE << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */ +#define MXC_V_GCR_RSTR0_DMA_BUSY ((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value */ +#define MXC_S_GCR_RSTR0_DMA_BUSY (MXC_V_GCR_RSTR0_DMA_BUSY << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */ + +#define MXC_F_GCR_RSTR0_WDT_POS 1 /**< RSTR0_WDT Position */ +#define MXC_F_GCR_RSTR0_WDT ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */ + +#define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */ +#define MXC_F_GCR_RSTR0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */ + +#define MXC_F_GCR_RSTR0_GPIO1_POS 3 /**< RSTR0_GPIO1 Position */ +#define MXC_F_GCR_RSTR0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO1_POS)) /**< RSTR0_GPIO1 Mask */ + +#define MXC_F_GCR_RSTR0_TIMER0_POS 5 /**< RSTR0_TIMER0 Position */ +#define MXC_F_GCR_RSTR0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */ + +#define MXC_F_GCR_RSTR0_TIMER1_POS 6 /**< RSTR0_TIMER1 Position */ +#define MXC_F_GCR_RSTR0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */ + +#define MXC_F_GCR_RSTR0_TIMER2_POS 7 /**< RSTR0_TIMER2 Position */ +#define MXC_F_GCR_RSTR0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */ + +#define MXC_F_GCR_RSTR0_TIMER3_POS 8 /**< RSTR0_TIMER3 Position */ +#define MXC_F_GCR_RSTR0_TIMER3 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER3_POS)) /**< RSTR0_TIMER3 Mask */ + +#define MXC_F_GCR_RSTR0_UART0_POS 11 /**< RSTR0_UART0 Position */ +#define MXC_F_GCR_RSTR0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */ + +#define MXC_F_GCR_RSTR0_SPI0_POS 13 /**< RSTR0_SPI0 Position */ +#define MXC_F_GCR_RSTR0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask */ + +#define MXC_F_GCR_RSTR0_SPI1_POS 14 /**< RSTR0_SPI1 Position */ +#define MXC_F_GCR_RSTR0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask */ + +#define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */ +#define MXC_F_GCR_RSTR0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask */ + +#define MXC_F_GCR_RSTR0_CRYPTO_POS 18 /**< RSTR0_CRYPTO Position */ +#define MXC_F_GCR_RSTR0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_CRYPTO_POS)) /**< RSTR0_CRYPTO Mask */ + +#define MXC_F_GCR_RSTR0_SMPHR_POS 22 /**< RSTR0_SMPHR Position */ +#define MXC_F_GCR_RSTR0_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SMPHR_POS)) /**< RSTR0_SMPHR Mask */ + +#define MXC_F_GCR_RSTR0_TRNG_POS 24 /**< RSTR0_TRNG Position */ +#define MXC_F_GCR_RSTR0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TRNG_POS)) /**< RSTR0_TRNG Mask */ + +#define MXC_F_GCR_RSTR0_SRST_POS 29 /**< RSTR0_SRST Position */ +#define MXC_F_GCR_RSTR0_SRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask */ + +#define MXC_F_GCR_RSTR0_PRST_POS 30 /**< RSTR0_PRST Position */ +#define MXC_F_GCR_RSTR0_PRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask */ + +#define MXC_F_GCR_RSTR0_SYSTEM_POS 31 /**< RSTR0_SYSTEM Position */ +#define MXC_F_GCR_RSTR0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */ + +/**@} end of group GCR_RSTR0_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_CLKCN GCR_CLKCN + * @brief Clock Control. + * @{ + */ +#define MXC_F_GCR_CLKCN_PSC_POS 6 /**< CLKCN_PSC Position */ +#define MXC_F_GCR_CLKCN_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) /**< CLKCN_PSC Mask */ +#define MXC_V_GCR_CLKCN_PSC_DIV1 ((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value */ +#define MXC_S_GCR_CLKCN_PSC_DIV1 (MXC_V_GCR_CLKCN_PSC_DIV1 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV1 Setting */ +#define MXC_V_GCR_CLKCN_PSC_DIV2 ((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value */ +#define MXC_S_GCR_CLKCN_PSC_DIV2 (MXC_V_GCR_CLKCN_PSC_DIV2 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV2 Setting */ +#define MXC_V_GCR_CLKCN_PSC_DIV4 ((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value */ +#define MXC_S_GCR_CLKCN_PSC_DIV4 (MXC_V_GCR_CLKCN_PSC_DIV4 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV4 Setting */ +#define MXC_V_GCR_CLKCN_PSC_DIV8 ((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value */ +#define MXC_S_GCR_CLKCN_PSC_DIV8 (MXC_V_GCR_CLKCN_PSC_DIV8 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV8 Setting */ +#define MXC_V_GCR_CLKCN_PSC_DIV16 ((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */ +#define MXC_S_GCR_CLKCN_PSC_DIV16 (MXC_V_GCR_CLKCN_PSC_DIV16 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting \ + */ +#define MXC_V_GCR_CLKCN_PSC_DIV32 ((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */ +#define MXC_S_GCR_CLKCN_PSC_DIV32 (MXC_V_GCR_CLKCN_PSC_DIV32 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting \ + */ +#define MXC_V_GCR_CLKCN_PSC_DIV64 ((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */ +#define MXC_S_GCR_CLKCN_PSC_DIV64 (MXC_V_GCR_CLKCN_PSC_DIV64 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting \ + */ +#define MXC_V_GCR_CLKCN_PSC_DIV128 ((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */ +#define MXC_S_GCR_CLKCN_PSC_DIV128 \ + (MXC_V_GCR_CLKCN_PSC_DIV128 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */ + +#define MXC_F_GCR_CLKCN_CLKSEL_POS 9 /**< CLKCN_CLKSEL Position */ +#define MXC_F_GCR_CLKCN_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */ +#define MXC_V_GCR_CLKCN_CLKSEL_HIRC ((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */ +#define MXC_S_GCR_CLKCN_CLKSEL_HIRC \ + (MXC_V_GCR_CLKCN_CLKSEL_HIRC << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */ +#define MXC_V_GCR_CLKCN_CLKSEL_LIRC8 ((uint32_t)0x3UL) /**< CLKCN_CLKSEL_LIRC8 Value */ +#define MXC_S_GCR_CLKCN_CLKSEL_LIRC8 \ + (MXC_V_GCR_CLKCN_CLKSEL_LIRC8 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_LIRC8 Setting */ +#define MXC_V_GCR_CLKCN_CLKSEL_HIRC8 ((uint32_t)0x5UL) /**< CLKCN_CLKSEL_HIRC8 Value */ +#define MXC_S_GCR_CLKCN_CLKSEL_HIRC8 \ + (MXC_V_GCR_CLKCN_CLKSEL_HIRC8 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC8 Setting */ + +#define MXC_F_GCR_CLKCN_CKRDY_POS 13 /**< CLKCN_CKRDY Position */ +#define MXC_F_GCR_CLKCN_CKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */ +#define MXC_V_GCR_CLKCN_CKRDY_BUSY ((uint32_t)0x0UL) /**< CLKCN_CKRDY_BUSY Value */ +#define MXC_S_GCR_CLKCN_CKRDY_BUSY \ + (MXC_V_GCR_CLKCN_CKRDY_BUSY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */ +#define MXC_V_GCR_CLKCN_CKRDY_READY ((uint32_t)0x1UL) /**< CLKCN_CKRDY_READY Value */ +#define MXC_S_GCR_CLKCN_CKRDY_READY \ + (MXC_V_GCR_CLKCN_CKRDY_READY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */ + +#define MXC_F_GCR_CLKCN_HIRC_EN_POS 18 /**< CLKCN_HIRC_EN Position */ +#define MXC_F_GCR_CLKCN_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */ +#define MXC_V_GCR_CLKCN_HIRC_EN_DIS ((uint32_t)0x0UL) /**< CLKCN_HIRC_EN_DIS Value */ +#define MXC_S_GCR_CLKCN_HIRC_EN_DIS \ + (MXC_V_GCR_CLKCN_HIRC_EN_DIS << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */ +#define MXC_V_GCR_CLKCN_HIRC_EN_EN ((uint32_t)0x1UL) /**< CLKCN_HIRC_EN_EN Value */ +#define MXC_S_GCR_CLKCN_HIRC_EN_EN \ + (MXC_V_GCR_CLKCN_HIRC_EN_EN << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */ + +#define MXC_F_GCR_CLKCN_HIRC8M_EN_POS 20 /**< CLKCN_HIRC8M_EN Position */ +#define MXC_F_GCR_CLKCN_HIRC8M_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_EN_POS)) /**< CLKCN_HIRC8M_EN Mask */ + +#define MXC_F_GCR_CLKCN_HIRC8M_VS_POS 21 /**< CLKCN_HIRC8M_VS Position */ +#define MXC_F_GCR_CLKCN_HIRC8M_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_VS_POS)) /**< CLKCN_HIRC8M_VS Mask */ +#define MXC_V_GCR_CLKCN_HIRC8M_VS_VCOR ((uint32_t)0x0UL) /**< CLKCN_HIRC8M_VS_VCOR Value */ +#define MXC_S_GCR_CLKCN_HIRC8M_VS_VCOR \ + (MXC_V_GCR_CLKCN_HIRC8M_VS_VCOR << MXC_F_GCR_CLKCN_HIRC8M_VS_POS) /**< CLKCN_HIRC8M_VS_VCOR Setting */ +#define MXC_V_GCR_CLKCN_HIRC8M_VS_1V ((uint32_t)0x1UL) /**< CLKCN_HIRC8M_VS_1V Value */ +#define MXC_S_GCR_CLKCN_HIRC8M_VS_1V \ + (MXC_V_GCR_CLKCN_HIRC8M_VS_1V << MXC_F_GCR_CLKCN_HIRC8M_VS_POS) /**< CLKCN_HIRC8M_VS_1V Setting */ + +#define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26 /**< CLKCN_HIRC_RDY Position */ +#define MXC_F_GCR_CLKCN_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */ +#define MXC_V_GCR_CLKCN_HIRC_RDY_NOT ((uint32_t)0x0UL) /**< CLKCN_HIRC_RDY_NOT Value */ +#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT \ + (MXC_V_GCR_CLKCN_HIRC_RDY_NOT << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */ +#define MXC_V_GCR_CLKCN_HIRC_RDY_READY ((uint32_t)0x1UL) /**< CLKCN_HIRC_RDY_READY Value */ +#define MXC_S_GCR_CLKCN_HIRC_RDY_READY \ + (MXC_V_GCR_CLKCN_HIRC_RDY_READY << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */ + +#define MXC_F_GCR_CLKCN_HIRC8M_RDY_POS 28 /**< CLKCN_HIRC8M_RDY Position */ +#define MXC_F_GCR_CLKCN_HIRC8M_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_RDY_POS)) /**< CLKCN_HIRC8M_RDY Mask */ + +#define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */ +#define MXC_F_GCR_CLKCN_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY Mask */ + +/**@} end of group GCR_CLKCN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PM GCR_PM + * @brief Power Management. + * @{ + */ +#define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ +#define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ +#define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ +#define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ +#define MXC_V_GCR_PM_MODE_DEEPSLEEP ((uint32_t)0x2UL) /**< PM_MODE_DEEPSLEEP Value */ +#define MXC_S_GCR_PM_MODE_DEEPSLEEP \ + (MXC_V_GCR_PM_MODE_DEEPSLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_DEEPSLEEP Setting */ +#define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ +#define MXC_S_GCR_PM_MODE_SHUTDOWN \ + (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ +#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ +#define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ + +#define MXC_F_GCR_PM_GPIOWKEN_POS 4 /**< PM_GPIOWKEN Position */ +#define MXC_F_GCR_PM_GPIOWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */ +#define MXC_V_GCR_PM_GPIOWKEN_DIS ((uint32_t)0x0UL) /**< PM_GPIOWKEN_DIS Value */ +#define MXC_S_GCR_PM_GPIOWKEN_DIS \ + (MXC_V_GCR_PM_GPIOWKEN_DIS << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_DIS Setting */ +#define MXC_V_GCR_PM_GPIOWKEN_EN ((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value */ +#define MXC_S_GCR_PM_GPIOWKEN_EN (MXC_V_GCR_PM_GPIOWKEN_EN << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting \ + */ + +#define MXC_F_GCR_PM_HIRCPD_POS 15 /**< PM_HIRCPD Position */ +#define MXC_F_GCR_PM_HIRCPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */ +#define MXC_V_GCR_PM_HIRCPD_ACTIVE ((uint32_t)0x0UL) /**< PM_HIRCPD_ACTIVE Value */ +#define MXC_S_GCR_PM_HIRCPD_ACTIVE \ + (MXC_V_GCR_PM_HIRCPD_ACTIVE << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */ +#define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP ((uint32_t)0x1UL) /**< PM_HIRCPD_DEEPSLEEP Value */ +#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP \ + (MXC_V_GCR_PM_HIRCPD_DEEPSLEEP << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */ + +#define MXC_F_GCR_PM_HIRC8MPD_POS 17 /**< PM_HIRC8MPD Position */ +#define MXC_F_GCR_PM_HIRC8MPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRC8MPD_POS)) /**< PM_HIRC8MPD Mask */ + +/**@} end of group GCR_PM_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PCKDIV GCR_PCKDIV + * @brief Peripheral Clock Divider. + * @{ + */ +#define MXC_F_GCR_PCKDIV_PCF_POS 0 /**< PCKDIV_PCF Position */ +#define MXC_F_GCR_PCKDIV_PCF ((uint32_t)(0x7UL << MXC_F_GCR_PCKDIV_PCF_POS)) /**< PCKDIV_PCF Mask */ +#define MXC_V_GCR_PCKDIV_PCF_96MHZ ((uint32_t)0x2UL) /**< PCKDIV_PCF_96MHZ Value */ +#define MXC_S_GCR_PCKDIV_PCF_96MHZ \ + (MXC_V_GCR_PCKDIV_PCF_96MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_96MHZ Setting */ +#define MXC_V_GCR_PCKDIV_PCF_48MHZ ((uint32_t)0x3UL) /**< PCKDIV_PCF_48MHZ Value */ +#define MXC_S_GCR_PCKDIV_PCF_48MHZ \ + (MXC_V_GCR_PCKDIV_PCF_48MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_48MHZ Setting */ +#define MXC_V_GCR_PCKDIV_PCF_24MHZ ((uint32_t)0x4UL) /**< PCKDIV_PCF_24MHZ Value */ +#define MXC_S_GCR_PCKDIV_PCF_24MHZ \ + (MXC_V_GCR_PCKDIV_PCF_24MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_24MHZ Setting */ +#define MXC_V_GCR_PCKDIV_PCF_12MHZ ((uint32_t)0x5UL) /**< PCKDIV_PCF_12MHZ Value */ +#define MXC_S_GCR_PCKDIV_PCF_12MHZ \ + (MXC_V_GCR_PCKDIV_PCF_12MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_12MHZ Setting */ +#define MXC_V_GCR_PCKDIV_PCF_6MHZ ((uint32_t)0x6UL) /**< PCKDIV_PCF_6MHZ Value */ +#define MXC_S_GCR_PCKDIV_PCF_6MHZ \ + (MXC_V_GCR_PCKDIV_PCF_6MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_6MHZ Setting */ +#define MXC_V_GCR_PCKDIV_PCF_3MHZ ((uint32_t)0x7UL) /**< PCKDIV_PCF_3MHZ Value */ +#define MXC_S_GCR_PCKDIV_PCF_3MHZ \ + (MXC_V_GCR_PCKDIV_PCF_3MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_3MHZ Setting */ + +#define MXC_F_GCR_PCKDIV_PCFWEN_POS 3 /**< PCKDIV_PCFWEN Position */ +#define MXC_F_GCR_PCKDIV_PCFWEN ((uint32_t)(0x1UL << MXC_F_GCR_PCKDIV_PCFWEN_POS)) /**< PCKDIV_PCFWEN Mask */ +#define MXC_V_GCR_PCKDIV_PCFWEN_DISABLED ((uint32_t)0x0UL) /**< PCKDIV_PCFWEN_DISABLED Value */ +#define MXC_S_GCR_PCKDIV_PCFWEN_DISABLED \ + (MXC_V_GCR_PCKDIV_PCFWEN_DISABLED << MXC_F_GCR_PCKDIV_PCFWEN_POS) /**< PCKDIV_PCFWEN_DISABLED Setting */ +#define MXC_V_GCR_PCKDIV_PCFWEN_ENABLED ((uint32_t)0x1UL) /**< PCKDIV_PCFWEN_ENABLED Value */ +#define MXC_S_GCR_PCKDIV_PCFWEN_ENABLED \ + (MXC_V_GCR_PCKDIV_PCFWEN_ENABLED << MXC_F_GCR_PCKDIV_PCFWEN_POS) /**< PCKDIV_PCFWEN_ENABLED Setting */ + +#define MXC_F_GCR_PCKDIV_AONCD_POS 14 /**< PCKDIV_AONCD Position */ +#define MXC_F_GCR_PCKDIV_AONCD ((uint32_t)(0x3UL << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */ +#define MXC_V_GCR_PCKDIV_AONCD_DIV_4 ((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */ +#define MXC_S_GCR_PCKDIV_AONCD_DIV_4 \ + (MXC_V_GCR_PCKDIV_AONCD_DIV_4 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */ +#define MXC_V_GCR_PCKDIV_AONCD_DIV_8 ((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */ +#define MXC_S_GCR_PCKDIV_AONCD_DIV_8 \ + (MXC_V_GCR_PCKDIV_AONCD_DIV_8 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */ +#define MXC_V_GCR_PCKDIV_AONCD_DIV_16 ((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */ +#define MXC_S_GCR_PCKDIV_AONCD_DIV_16 \ + (MXC_V_GCR_PCKDIV_AONCD_DIV_16 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */ +#define MXC_V_GCR_PCKDIV_AONCD_DIV_32 ((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */ +#define MXC_S_GCR_PCKDIV_AONCD_DIV_32 \ + (MXC_V_GCR_PCKDIV_AONCD_DIV_32 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */ + +/**@} end of group GCR_PCKDIV_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PERCKCN0 GCR_PERCKCN0 + * @brief Peripheral Clock Disable. + * @{ + */ +#define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0 /**< PERCKCN0_GPIO0D Position */ +#define MXC_F_GCR_PERCKCN0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D Mask */ +#define MXC_V_GCR_PERCKCN0_GPIO0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_GPIO0D_EN Value */ +#define MXC_S_GCR_PERCKCN0_GPIO0D_EN \ + (MXC_V_GCR_PERCKCN0_GPIO0D_EN << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */ +#define MXC_V_GCR_PERCKCN0_GPIO0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_GPIO0D_DIS Value */ +#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS \ + (MXC_V_GCR_PERCKCN0_GPIO0D_DIS << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */ + +#define MXC_F_GCR_PERCKCN0_GPIO1D_POS 1 /**< PERCKCN0_GPIO1D Position */ +#define MXC_F_GCR_PERCKCN0_GPIO1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO1D_POS)) /**< PERCKCN0_GPIO1D Mask */ + +#define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */ +#define MXC_F_GCR_PERCKCN0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */ + +#define MXC_F_GCR_PERCKCN0_SPI0D_POS 6 /**< PERCKCN0_SPI0D Position */ +#define MXC_F_GCR_PERCKCN0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */ + +#define MXC_F_GCR_PERCKCN0_SPI1D_POS 7 /**< PERCKCN0_SPI1D Position */ +#define MXC_F_GCR_PERCKCN0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */ + +#define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */ +#define MXC_F_GCR_PERCKCN0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D Mask */ + +#define MXC_F_GCR_PERCKCN0_I2C0D_POS 13 /**< PERCKCN0_I2C0D Position */ +#define MXC_F_GCR_PERCKCN0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */ + +#define MXC_F_GCR_PERCKCN0_CRYPTOD_POS 14 /**< PERCKCN0_CRYPTOD Position */ +#define MXC_F_GCR_PERCKCN0_CRYPTOD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_CRYPTOD_POS)) /**< PERCKCN0_CRYPTOD Mask */ + +#define MXC_F_GCR_PERCKCN0_T0D_POS 15 /**< PERCKCN0_T0D Position */ +#define MXC_F_GCR_PERCKCN0_T0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */ + +#define MXC_F_GCR_PERCKCN0_T1D_POS 16 /**< PERCKCN0_T1D Position */ +#define MXC_F_GCR_PERCKCN0_T1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */ + +#define MXC_F_GCR_PERCKCN0_T2D_POS 17 /**< PERCKCN0_T2D Position */ +#define MXC_F_GCR_PERCKCN0_T2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */ + +#define MXC_F_GCR_PERCKCN0_T3D_POS 18 /**< PERCKCN0_T3D Position */ +#define MXC_F_GCR_PERCKCN0_T3D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T3D_POS)) /**< PERCKCN0_T3D Mask */ + +/**@} end of group GCR_PERCKCN0_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_MEMCKCN GCR_MEMCKCN + * @brief Memory Clock Control Register. + * @{ + */ +#define MXC_F_GCR_MEMCKCN_FWS_POS 0 /**< MEMCKCN_FWS Position */ +#define MXC_F_GCR_MEMCKCN_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */ + +#define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 16 /**< MEMCKCN_SYSRAM0LS Position */ +#define MXC_F_GCR_MEMCKCN_SYSRAM0LS \ + ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< MEMCKCN_SYSRAM0LS Mask */ +#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */ +#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE \ + (MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE Setting */ +#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */ +#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \ + (MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \ + << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Setting */ + +#define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 17 /**< MEMCKCN_SYSRAM1LS Position */ +#define MXC_F_GCR_MEMCKCN_SYSRAM1LS \ + ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS Mask */ + +#define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 18 /**< MEMCKCN_SYSRAM2LS Position */ +#define MXC_F_GCR_MEMCKCN_SYSRAM2LS \ + ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS Mask */ + +#define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 19 /**< MEMCKCN_SYSRAM3LS Position */ +#define MXC_F_GCR_MEMCKCN_SYSRAM3LS \ + ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS Mask */ + +#define MXC_F_GCR_MEMCKCN_SYSRAM4LS_POS 20 /**< MEMCKCN_SYSRAM4LS Position */ +#define MXC_F_GCR_MEMCKCN_SYSRAM4LS \ + ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM4LS_POS)) /**< MEMCKCN_SYSRAM4LS Mask */ + +#define MXC_F_GCR_MEMCKCN_ICACHELS_POS 24 /**< MEMCKCN_ICACHELS Position */ +#define MXC_F_GCR_MEMCKCN_ICACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS Mask */ + +#define MXC_F_GCR_MEMCKCN_ROMLS_POS 29 /**< MEMCKCN_ROMLS Position */ +#define MXC_F_GCR_MEMCKCN_ROMLS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ROMLS_POS)) /**< MEMCKCN_ROMLS Mask */ + +/**@} end of group GCR_MEMCKCN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_MEMZCN GCR_MEMZCN + * @brief Memory Zeroize Control. + * @{ + */ +#define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0 /**< MEMZCN_SRAM0Z Position */ +#define MXC_F_GCR_MEMZCN_SRAM0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */ +#define MXC_V_GCR_MEMZCN_SRAM0Z_NOP ((uint32_t)0x0UL) /**< MEMZCN_SRAM0Z_NOP Value */ +#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP \ + (MXC_V_GCR_MEMZCN_SRAM0Z_NOP << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */ +#define MXC_V_GCR_MEMZCN_SRAM0Z_START ((uint32_t)0x1UL) /**< MEMZCN_SRAM0Z_START Value */ +#define MXC_S_GCR_MEMZCN_SRAM0Z_START \ + (MXC_V_GCR_MEMZCN_SRAM0Z_START << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */ + +#define MXC_F_GCR_MEMZCN_SRAM1Z_POS 1 /**< MEMZCN_SRAM1Z Position */ +#define MXC_F_GCR_MEMZCN_SRAM1Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM1Z_POS)) /**< MEMZCN_SRAM1Z Mask */ + +#define MXC_F_GCR_MEMZCN_SRAM2Z_POS 2 /**< MEMZCN_SRAM2Z Position */ +#define MXC_F_GCR_MEMZCN_SRAM2Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM2Z_POS)) /**< MEMZCN_SRAM2Z Mask */ + +#define MXC_F_GCR_MEMZCN_SRAM3Z_POS 3 /**< MEMZCN_SRAM3Z Position */ +#define MXC_F_GCR_MEMZCN_SRAM3Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM3Z_POS)) /**< MEMZCN_SRAM3Z Mask */ + +#define MXC_F_GCR_MEMZCN_SRAM4Z_POS 4 /**< MEMZCN_SRAM4Z Position */ +#define MXC_F_GCR_MEMZCN_SRAM4Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM4Z_POS)) /**< MEMZCN_SRAM4Z Mask */ + +#define MXC_F_GCR_MEMZCN_ICACHEZ_POS 8 /**< MEMZCN_ICACHEZ Position */ +#define MXC_F_GCR_MEMZCN_ICACHEZ ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */ + +/**@} end of group GCR_MEMZCN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SYSST GCR_SYSST + * @brief System Status Register. + * @{ + */ +#define MXC_F_GCR_SYSST_ICECLOCK_POS 0 /**< SYSST_ICECLOCK Position */ +#define MXC_F_GCR_SYSST_ICECLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */ +#define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED ((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */ +#define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED \ + (MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting */ +#define MXC_V_GCR_SYSST_ICECLOCK_LOCKED ((uint32_t)0x1UL) /**< SYSST_ICECLOCK_LOCKED Value */ +#define MXC_S_GCR_SYSST_ICECLOCK_LOCKED \ + (MXC_V_GCR_SYSST_ICECLOCK_LOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting */ + +/**@} end of group GCR_SYSST_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_RSTR1 GCR_RSTR1 + * @brief Reset 1. + * @{ + */ +#define MXC_F_GCR_RSTR1_WDT1_POS 8 /**< RSTR1_WDT1 Position */ +#define MXC_F_GCR_RSTR1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_WDT1_POS)) /**< RSTR1_WDT1 Mask */ +#define MXC_V_GCR_RSTR1_WDT1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR1_WDT1_RESET_DONE Value */ +#define MXC_S_GCR_RSTR1_WDT1_RESET_DONE \ + (MXC_V_GCR_RSTR1_WDT1_RESET_DONE << MXC_F_GCR_RSTR1_WDT1_POS) /**< RSTR1_WDT1_RESET_DONE Setting */ +#define MXC_V_GCR_RSTR1_WDT1_BUSY ((uint32_t)0x1UL) /**< RSTR1_WDT1_BUSY Value */ +#define MXC_S_GCR_RSTR1_WDT1_BUSY \ + (MXC_V_GCR_RSTR1_WDT1_BUSY << MXC_F_GCR_RSTR1_WDT1_POS) /**< RSTR1_WDT1_BUSY Setting */ + +#define MXC_F_GCR_RSTR1_PUFC_POS 27 /**< RSTR1_PUFC Position */ +#define MXC_F_GCR_RSTR1_PUFC ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_PUFC_POS)) /**< RSTR1_PUFC Mask */ + +#define MXC_F_GCR_RSTR1_CSPIS_POS 28 /**< RSTR1_CSPIS Position */ +#define MXC_F_GCR_RSTR1_CSPIS ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_CSPIS_POS)) /**< RSTR1_CSPIS Mask */ + +/**@} end of group GCR_RSTR1_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PERCKCN1 GCR_PERCKCN1 + * @brief Peripheral Clock Disable. + * @{ + */ +#define MXC_F_GCR_PERCKCN1_TRNGD_POS 2 /**< PERCKCN1_TRNGD Position */ +#define MXC_F_GCR_PERCKCN1_TRNGD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_TRNGD_POS)) /**< PERCKCN1_TRNGD Mask */ +#define MXC_V_GCR_PERCKCN1_TRNGD_EN ((uint32_t)0x0UL) /**< PERCKCN1_TRNGD_EN Value */ +#define MXC_S_GCR_PERCKCN1_TRNGD_EN \ + (MXC_V_GCR_PERCKCN1_TRNGD_EN << MXC_F_GCR_PERCKCN1_TRNGD_POS) /**< PERCKCN1_TRNGD_EN Setting */ +#define MXC_V_GCR_PERCKCN1_TRNGD_DIS ((uint32_t)0x1UL) /**< PERCKCN1_TRNGD_DIS Value */ +#define MXC_S_GCR_PERCKCN1_TRNGD_DIS \ + (MXC_V_GCR_PERCKCN1_TRNGD_DIS << MXC_F_GCR_PERCKCN1_TRNGD_POS) /**< PERCKCN1_TRNGD_DIS Setting */ + +#define MXC_F_GCR_PERCKCN1_PUFCD_POS 3 /**< PERCKCN1_PUFCD Position */ +#define MXC_F_GCR_PERCKCN1_PUFCD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_PUFCD_POS)) /**< PERCKCN1_PUFCD Mask */ + +#define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */ +#define MXC_F_GCR_PERCKCN1_ICACHED ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED Mask */ + +#define MXC_F_GCR_PERCKCN1_CSPISD_POS 30 /**< PERCKCN1_CSPISD Position */ +#define MXC_F_GCR_PERCKCN1_CSPISD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_CSPISD_POS)) /**< PERCKCN1_CSPISD Mask */ + +/**@} end of group GCR_PERCKCN1_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_EVTEN GCR_EVTEN + * @brief Event Enable Register. + * @{ + */ +#define MXC_F_GCR_EVTEN_CPU0DMAEVENT_POS 0 /**< EVTEN_CPU0DMAEVENT Position */ +#define MXC_F_GCR_EVTEN_CPU0DMAEVENT \ + ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0DMAEVENT_POS)) /**< EVTEN_CPU0DMAEVENT Mask */ + +#define MXC_F_GCR_EVTEN_CPU0RXEVENT_POS 1 /**< EVTEN_CPU0RXEVENT Position */ +#define MXC_F_GCR_EVTEN_CPU0RXEVENT \ + ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0RXEVENT_POS)) /**< EVTEN_CPU0RXEVENT Mask */ + +#define MXC_F_GCR_EVTEN_CPU0TXEVENT_POS 2 /**< EVTEN_CPU0TXEVENT Position */ +#define MXC_F_GCR_EVTEN_CPU0TXEVENT \ + ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0TXEVENT_POS)) /**< EVTEN_CPU0TXEVENT Mask */ + +/**@} end of group GCR_EVTEN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_REVISION GCR_REVISION + * @brief Revision Register. + * @{ + */ +#define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ +#define MXC_F_GCR_REVISION_REVISION \ + ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ + +/**@} end of group GCR_REVISION_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SYSSIE GCR_SYSSIE + * @brief System Status Interrupt Enable Register. + * @{ + */ +#define MXC_F_GCR_SYSSIE_ICEULIE_POS 0 /**< SYSSIE_ICEULIE Position */ +#define MXC_F_GCR_SYSSIE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */ +#define MXC_V_GCR_SYSSIE_ICEULIE_DIS ((uint32_t)0x0UL) /**< SYSSIE_ICEULIE_DIS Value */ +#define MXC_S_GCR_SYSSIE_ICEULIE_DIS \ + (MXC_V_GCR_SYSSIE_ICEULIE_DIS << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_DIS Setting */ +#define MXC_V_GCR_SYSSIE_ICEULIE_EN ((uint32_t)0x1UL) /**< SYSSIE_ICEULIE_EN Value */ +#define MXC_S_GCR_SYSSIE_ICEULIE_EN \ + (MXC_V_GCR_SYSSIE_ICEULIE_EN << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_EN Setting */ + +/**@} end of group GCR_SYSSIE_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCERR GCR_ECCERR + * @brief ECC Error Register + * @{ + */ +#define MXC_F_GCR_ECCERR_SYSRAM0ECCERR_POS 0 /**< ECCERR_SYSRAM0ECCERR Position */ +#define MXC_F_GCR_ECCERR_SYSRAM0ECCERR \ + ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM0ECCERR_POS)) /**< ECCERR_SYSRAM0ECCERR Mask */ + +#define MXC_F_GCR_ECCERR_SYSRAM1ECCERR_POS 1 /**< ECCERR_SYSRAM1ECCERR Position */ +#define MXC_F_GCR_ECCERR_SYSRAM1ECCERR \ + ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM1ECCERR_POS)) /**< ECCERR_SYSRAM1ECCERR Mask */ + +#define MXC_F_GCR_ECCERR_SYSRAM2ECCERR_POS 2 /**< ECCERR_SYSRAM2ECCERR Position */ +#define MXC_F_GCR_ECCERR_SYSRAM2ECCERR \ + ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM2ECCERR_POS)) /**< ECCERR_SYSRAM2ECCERR Mask */ + +#define MXC_F_GCR_ECCERR_SYSRAM3ECCERR_POS 3 /**< ECCERR_SYSRAM3ECCERR Position */ +#define MXC_F_GCR_ECCERR_SYSRAM3ECCERR \ + ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM3ECCERR_POS)) /**< ECCERR_SYSRAM3ECCERR Mask */ + +#define MXC_F_GCR_ECCERR_SYSRAM4ECCERR_POS 4 /**< ECCERR_SYSRAM4ECCERR Position */ +#define MXC_F_GCR_ECCERR_SYSRAM4ECCERR \ + ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM4ECCERR_POS)) /**< ECCERR_SYSRAM4ECCERR Mask */ + +/**@} end of group GCR_ECCERR_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCNDED GCR_ECCNDED + * @brief ECC Not Double Error Detect Register + * @{ + */ +#define MXC_F_GCR_ECCNDED_SYSRAM0ECCNDED_POS 0 /**< ECCNDED_SYSRAM0ECCNDED Position */ +#define MXC_F_GCR_ECCNDED_SYSRAM0ECCNDED \ + ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM0ECCNDED_POS)) /**< ECCNDED_SYSRAM0ECCNDED Mask */ + +#define MXC_F_GCR_ECCNDED_SYSRAM1ECCNDED_POS 1 /**< ECCNDED_SYSRAM1ECCNDED Position */ +#define MXC_F_GCR_ECCNDED_SYSRAM1ECCNDED \ + ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM1ECCNDED_POS)) /**< ECCNDED_SYSRAM1ECCNDED Mask */ + +#define MXC_F_GCR_ECCNDED_SYSRAM2ECCNDED_POS 2 /**< ECCNDED_SYSRAM2ECCNDED Position */ +#define MXC_F_GCR_ECCNDED_SYSRAM2ECCNDED \ + ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM2ECCNDED_POS)) /**< ECCNDED_SYSRAM2ECCNDED Mask */ + +#define MXC_F_GCR_ECCNDED_SYSRAM3ECCNDED_POS 3 /**< ECCNDED_SYSRAM3ECCNDED Position */ +#define MXC_F_GCR_ECCNDED_SYSRAM3ECCNDED \ + ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM3ECCNDED_POS)) /**< ECCNDED_SYSRAM3ECCNDED Mask */ + +#define MXC_F_GCR_ECCNDED_SYSRAM4ECCNDED_POS 4 /**< ECCNDED_SYSRAM4ECCNDED Position */ +#define MXC_F_GCR_ECCNDED_SYSRAM4ECCNDED \ + ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM4ECCNDED_POS)) /**< ECCNDED_SYSRAM4ECCNDED Mask */ + +/**@} end of group GCR_ECCNDED_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCIRQEN GCR_ECCIRQEN + * @brief ECC IRQ Enable Register + * @{ + */ +#define MXC_F_GCR_ECCIRQEN_ECCERAD_POS 0 /**< ECCIRQEN_ECCERAD Position */ +#define MXC_F_GCR_ECCIRQEN_ECCERAD \ + ((uint32_t)(0x7FFFFFFFUL << MXC_F_GCR_ECCIRQEN_ECCERAD_POS)) /**< ECCIRQEN_ECCERAD Mask */ + +/**@} end of group GCR_ECCIRQEN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCERRAD GCR_ECCERRAD + * @brief ECC Error Address Register + * @{ + */ +#define MXC_F_GCR_ECCERRAD_ECCERAD_POS 0 /**< ECCERRAD_ECCERAD Position */ +#define MXC_F_GCR_ECCERRAD_ECCERAD \ + ((uint32_t)(0x7FFFFFFFUL << MXC_F_GCR_ECCERRAD_ECCERAD_POS)) /**< ECCERRAD_ECCERAD Mask */ + +/**@} end of group GCR_ECCERRAD_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GCR_REGS_H_ */ diff --git a/contrib/loaders/flash/max32xxx/max32xxx.inc b/contrib/loaders/flash/max32xxx/max32xxx.inc deleted file mode 100644 index 442165d0d..000000000 --- a/contrib/loaders/flash/max32xxx/max32xxx.inc +++ /dev/null @@ -1,6 +0,0 @@ -/* Autogenerated with ../../../../src/helper/bin2char.sh */ -0xdf,0xf8,0x44,0x40,0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x1a,0xd0,0x47,0x68, -0x47,0x45,0xf7,0xd0,0x22,0x60,0x02,0xf1,0x04,0x02,0x57,0xf8,0x04,0x8b,0xc4,0xf8, -0x30,0x80,0xa5,0x68,0x45,0xf0,0x01,0x05,0xa5,0x60,0xd4,0xf8,0x08,0x80,0x18,0xf0, -0x01,0x0f,0xfa,0xd1,0x8f,0x42,0x28,0xbf,0x00,0xf1,0x08,0x07,0x47,0x60,0x01,0x3b, -0x03,0xb1,0xdf,0xe7,0x00,0xbe,0x00,0xbf,0x00,0x00,0x00,0x40, diff --git a/contrib/loaders/flash/max32xxx/max32xxx.s b/contrib/loaders/flash/max32xxx/max32xxx.s deleted file mode 100644 index 38a4f12c3..000000000 --- a/contrib/loaders/flash/max32xxx/max32xxx.s +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/*************************************************************************** - * Copyright (C) 2016 by Maxim Integrated * - * Kevin Gillespie +#else +#define printf(...) +#endif + +/***** Definitions *****/ +#define MXC_BASE_TPU ((uint32_t)0x40001000UL) +#define MXC_TPU ((struct mxc_tpu_regs *)MXC_BASE_TPU) +#define MXC_BASE_GCR ((uint32_t)0x40000000UL) +#define MXC_GCR ((struct mxc_gcr_regs *)MXC_BASE_GCR) + +/******************************************************************************/ +#define getbyte(temp8) \ +/* Wait for the Read FIFO to not equal the Write FIFO */ \ + do { while (*read_ptr == *write_ptr); \ + temp8 = **read_ptr; \ +/* Increment and wrap around the read pointer */ \ + if ((*read_ptr + 1) >= (uint8_t *)(work_end - 8 - 256)) { \ + *read_ptr = (uint8_t *)(work_start + 8); \ + } else { \ + (*read_ptr)++; \ + } \ + len--; \ + addr++; } while (0) + +/******************************************************************************/ +#ifndef ALGO_TEST +__attribute__ ((naked, section(".algo"))) +#endif +void algo_write(uint8_t *work_start, uint8_t *work_end, uint32_t len, uint32_t addr) +{ + printf(" > %s starting\n", __func__); + + volatile uint8_t * (*write_ptr) = (volatile uint8_t **)work_start; + volatile uint8_t * (*read_ptr) = (volatile uint8_t **)(work_start + 4); + uint32_t *flc_base = (uint32_t *)(work_end - 4 - 128); + uint32_t *options = (uint32_t *)(work_end - 8 - 128); + uint32_t *enc_buffer = (uint32_t *)(work_end - 8 - 256); + uint8_t temp8; + uint32_t addr_save; + int i; + struct mxc_flc_regs *MXC_FLC = (struct mxc_flc_regs *)*flc_base; + + printf(" > w%08x r%08x o%08x f%08x b%08x b%08x\n", + (uint32_t)write_ptr, (uint32_t)read_ptr, (uint32_t)*options, (uint32_t)*flc_base, + (uint32_t)enc_buffer, (uint32_t)(enc_buffer + 256)); + + if (*options & OPTIONS_ENC) { + /* Enable Memory Protection */ + MXC_GCR->scon |= MXC_F_GCR_SCON_MEMPROT_EN; + + /* Set the keysize */ + if (*options & OPTIONS_KEYSIZE) + MXC_GCR->scon |= MXC_F_GCR_SCON_MEMPROT_KEYSZ; + else + MXC_GCR->scon &= ~(MXC_F_GCR_SCON_MEMPROT_KEYSZ); + } else { + /* Disable memory protection */ + MXC_GCR->scon &= ~MXC_F_GCR_SCON_MEMPROT_EN; + } + + if (*options & OPTIONS_ENC) { + /* Setup the AES */ + + /* Enable CRYPTO clock */ + if ((MXC_GCR->clkcn & MXC_F_GCR_CLKCN_HIRC_EN) == 0) + MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC_EN; + + /* Disable CRYPTO clock gate */ + if (MXC_GCR->perckcn0 & MXC_F_GCR_PERCKCN0_CRYPTOD) + MXC_GCR->perckcn0 &= ~(MXC_F_GCR_PERCKCN0_CRYPTOD); + + /* Reset Crypto block and clear state */ + MXC_TPU->ctrl = MXC_F_TPU_CTRL_RST; + + /* Set the legacy bit */ + MXC_TPU->ctrl |= MXC_F_TPU_CTRL_FLAG_MODE; + + /* Byte swap the input and output */ + MXC_TPU->ctrl |= MXC_F_TPU_CTRL_BSO; + MXC_TPU->ctrl |= MXC_F_TPU_CTRL_BSI; + } + + while (len) { + if ((*options & OPTIONS_128) == 0) { + /* Save the current address before we read from the working area */ + addr_save = addr; + + /* 32-bit write */ + MXC_FLC->cn |= MXC_F_FLC_CN_WDTH; + + enc_buffer[0] = 0; + for (i = 0; i < 4; i++) { + /* Get data from the working area, pad with 0xFF */ + if (len) { + getbyte(temp8); + __asm("nop\n"); + } else { + temp8 = 0xFF; + __asm("nop\n"); + } + enc_buffer[0] |= (temp8 << (i * 8)); + } + + /* 32-bit write */ + MXC_FLC->cn |= MXC_F_FLC_CN_WDTH; + + MXC_FLC->addr = addr_save; + MXC_FLC->data[0] = enc_buffer[0]; + + /* Enable the write */ + MXC_FLC->cn |= MXC_F_FLC_CN_WR; + + /* Wait for the operation to complete */ + do {} while (MXC_FLC->cn & MXC_F_FLC_CN_WR); + + /* Check access violations */ + if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) { + MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF; + #ifndef ALGO_TEST + #ifdef __riscv + __asm("ebreak\n"); + #else + __asm("bkpt\n"); + #endif + #else + printf(" > Error writing to flash\n"); + return; + #endif + } + } else { + /* Save the current address before we read from the working area */ + addr_save = addr; + + /* Fill the buffer with the plain text data from the working area */ + for (i = 0; i < 4; i++) { + /* Get data from the working area, pad with 0xFF */ + enc_buffer[i] = 0; + if (len) { + getbyte(temp8); + __asm("nop\n"); + } else { + temp8 = 0xFF; + __asm("nop\n"); + } + enc_buffer[i] |= (temp8 << (0)); + /* Get data from the working area, pad with 0xFF */ + if (len) { + getbyte(temp8); + __asm("nop\n"); + } else { + temp8 = 0xFF; + __asm("nop\n"); + } + enc_buffer[i] |= (temp8 << (8)); + /* Get data from the working area, pad with 0xFF */ + if (len) { + getbyte(temp8); + __asm("nop\n"); + } else { + temp8 = 0xFF; + __asm("nop\n"); + } + enc_buffer[i] |= (temp8 << (16)); + /* Get data from the working area, pad with 0xFF */ + if (len) { + getbyte(temp8); + __asm("nop\n"); + } else { + temp8 = 0xFF; + __asm("nop\n"); + } + enc_buffer[i] |= (temp8 << (24)); + } + + if (*options & OPTIONS_ENC) { + /* XOR data with the address */ + for (i = 0; i < 4; i++) { + if (*options & OPTIONS_RELATIVE_XOR) + enc_buffer[i] ^= ((addr_save & 0x00FFFFFF) + i * 4); + else + enc_buffer[i] ^= (addr_save + i * 4); + } + + /* Encrypt the plain text + * Clear interrupt flags*/ + MXC_TPU->ctrl |= MXC_F_TPU_CTRL_CPH_DONE; + + MXC_TPU->cipher_ctrl = ((0x0 << MXC_F_TPU_CIPHER_CTRL_MODE_POS) | + (0x0 << MXC_F_TPU_CIPHER_CTRL_ENC_POS)); + + if (*options & OPTIONS_KEYSIZE) { + /* ECB, AES-256, encrypt */ + MXC_TPU->cipher_ctrl |= + (0x3 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS); + } else { + /* ECB, AES-128, encrypt */ + MXC_TPU->cipher_ctrl |= + (0x1 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS); + } + + /* Set the key source */ + MXC_TPU->cipher_ctrl = + ((MXC_TPU->cipher_ctrl & ~MXC_F_TPU_CIPHER_CTRL_SRC) | + (0x3 << MXC_F_TPU_CIPHER_CTRL_SRC_POS)); + + /* Copy data to start the operation */ + MXC_TPU->din[0] = enc_buffer[0]; + MXC_TPU->din[1] = enc_buffer[1]; + MXC_TPU->din[2] = enc_buffer[2]; + MXC_TPU->din[3] = enc_buffer[3]; + + /* Wait until operation is complete */ + do {} while (!(MXC_TPU->ctrl & MXC_F_TPU_CTRL_CPH_DONE)); + + /* Copy the data out */ + enc_buffer[0] = MXC_TPU->dout[0]; + enc_buffer[1] = MXC_TPU->dout[1]; + enc_buffer[2] = MXC_TPU->dout[2]; + enc_buffer[3] = MXC_TPU->dout[3]; + } + + /* 128-bit write */ + MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH; + + MXC_FLC->addr = addr_save; + MXC_FLC->data[0] = enc_buffer[0]; + MXC_FLC->data[1] = enc_buffer[1]; + MXC_FLC->data[2] = enc_buffer[2]; + MXC_FLC->data[3] = enc_buffer[3]; + + /* Enable the write */ + MXC_FLC->cn |= MXC_F_FLC_CN_WR; + + /* Wait for the operation to complete */ + do {} while (MXC_FLC->cn & MXC_F_FLC_CN_WR); + + /* Check access violations */ + if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) { + MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF; + #ifndef ALGO_TEST + #ifdef __riscv + __asm("ebreak\n"); + #else + __asm("bkpt\n"); + #endif + printf(" > Error writing to flash\n"); + return; + #endif + } + } + } + + #ifndef ALGO_TEST + #ifdef __riscv + __asm("ebreak\n"); + #else + __asm("bkpt\n"); + #endif + #else + printf(" > %s returning\n", __func__); + return; + #endif +} diff --git a/contrib/loaders/flash/max32xxx/max32xxx_write_arm.inc b/contrib/loaders/flash/max32xxx/max32xxx_write_arm.inc new file mode 100644 index 000000000..cdc373071 --- /dev/null +++ b/contrib/loaders/flash/max32xxx/max32xxx_write_arm.inc @@ -0,0 +1,57 @@ +/* Autogenerated with ../../../../src/helper/bin2char.sh */ +0x51,0xe9,0x22,0x54,0x15,0xf0,0x02,0x0f,0x4f,0xf0,0x80,0x45,0x00,0x93,0xa1,0xf5, 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+ ***************************************************************************/ + +#ifndef _TPU_REGS_H_ +#define _TPU_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__ICCARM__) +#pragma system_include +#endif + +/*/ @cond */ +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/*/ @endcond */ + +/* **** Definitions **** */ + +/** + * @ingroup tpu + * @defgroup tpu_registers Registers + * @brief Registers, Bit Masks and Bit Positions for the TPU Peripheral Module. + * @description The Trust Protection Unit used to assist the computationally intensive operations of several common + * cryptographic algorithms. + */ + +/** + * @ingroup tpu_registers + * Structure type to access the TPU Registers. + */ +struct mxc_tpu_regs { + __IO uint32_t ctrl; /**< \b 0x00:<\tt> TPU CTRL Register */ + __IO uint32_t cipher_ctrl; /**< \b 0x04:<\tt> TPU CIPHER_CTRL Register */ + __IO uint32_t hash_ctrl; /**< \b 0x08:<\tt> TPU HASH_CTRL Register */ + __IO uint32_t crc_ctrl; /**< \b 0x0C:<\tt> TPU CRC_CTRL Register */ + __IO uint32_t dma_src; /**< \b 0x10:<\tt> TPU DMA_SRC Register */ + __IO uint32_t dma_dest; /**< \b 0x14:<\tt> TPU DMA_DEST Register */ + __IO uint32_t dma_cnt; /**< \b 0x18:<\tt> TPU DMA_CNT Register */ + __IO uint32_t maa_ctrl; /**< \b 0x1C:<\tt> TPU MAA_CTRL Register */ + __O uint32_t din[4]; /**< \b 0x20:<\tt> TPU DIN Register */ + __I uint32_t dout[4]; /**< \b 0x30:<\tt> TPU DOUT Register */ + __IO uint32_t crc_poly; /**< \b 0x40:<\tt> TPU CRC_POLY Register */ + __IO uint32_t crc_val; /**< \b 0x44:<\tt> TPU CRC_VAL Register */ + __I uint32_t crc_prng; /**< \b 0x48:<\tt> TPU CRC_PRNG Register */ + __IO uint32_t ham_ecc; /**< \b 0x4C:<\tt> TPU HAM_ECC Register */ + __IO uint32_t cipher_init[4]; /**< \b 0x50:<\tt> TPU CIPHER_INIT Register */ + __O uint32_t cipher_key[8]; /**< \b 0x60:<\tt> TPU CIPHER_KEY Register */ + __IO uint32_t hash_digest[16]; /**< \b 0x80:<\tt> TPU HASH_DIGEST Register */ + __IO uint32_t hash_msg_sz[4]; /**< \b 0xC0:<\tt> TPU HASH_MSG_SZ Register */ + __IO uint32_t maa_maws; /**< \b 0xD0:<\tt> TPU MAA_MAWS Register */ +}; + +/* Register offsets for module TPU */ +/** + * @ingroup tpu_registers + * @defgroup TPU_Register_Offsets Register Offsets + * @brief TPU Peripheral Register Offsets from the TPU Base Peripheral Address. + * @{ + */ +#define MXC_R_TPU_CTRL ((uint32_t)0x00000000UL) /**< Offset from TPU Base Address: 0x0x000 */ +#define MXC_R_TPU_CIPHER_CTRL ((uint32_t)0x00000004UL) /**< Offset from TPU Base Address: 0x0x004 */ +#define MXC_R_TPU_HASH_CTRL ((uint32_t)0x00000008UL) /**< Offset from TPU Base Address: 0x0x008 */ +#define MXC_R_TPU_CRC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from TPU Base Address: 0x0x00C */ +#define MXC_R_TPU_DMA_SRC ((uint32_t)0x00000010UL) /**< Offset from TPU Base Address: 0x0x010 */ +#define MXC_R_TPU_DMA_DEST ((uint32_t)0x00000014UL) /**< Offset from TPU Base Address: 0x0x014 */ +#define MXC_R_TPU_DMA_CNT ((uint32_t)0x00000018UL) /**< Offset from TPU Base Address: 0x0x018 */ +#define MXC_R_TPU_MAA_CTRL ((uint32_t)0x0000001CUL) /**< Offset from TPU Base Address: 0x0x01C */ +#define MXC_R_TPU_DIN ((uint32_t)0x00000020UL) /**< Offset from TPU Base Address: 0x0x020 */ +#define MXC_R_TPU_DOUT ((uint32_t)0x00000030UL) /**< Offset from TPU Base Address: 0x0x030 */ +#define MXC_R_TPU_CRC_POLY ((uint32_t)0x00000040UL) /**< Offset from TPU Base Address: 0x0x040 */ +#define MXC_R_TPU_CRC_VAL ((uint32_t)0x00000044UL) /**< Offset from TPU Base Address: 0x0x044 */ +#define MXC_R_TPU_CRC_PRNG ((uint32_t)0x00000048UL) /**< Offset from TPU Base Address: 0x0x048 */ +#define MXC_R_TPU_HAM_ECC ((uint32_t)0x0000004CUL) /**< Offset from TPU Base Address: 0x0x04C */ +#define MXC_R_TPU_CIPHER_INIT ((uint32_t)0x00000050UL) /**< Offset from TPU Base Address: 0x0x050 */ +#define MXC_R_TPU_CIPHER_KEY ((uint32_t)0x00000060UL) /**< Offset from TPU Base Address: 0x0x060 */ +#define MXC_R_TPU_HASH_DIGEST ((uint32_t)0x00000080UL) /**< Offset from TPU Base Address: 0x0x080 */ +#define MXC_R_TPU_HASH_MSG_SZ ((uint32_t)0x000000C0UL) /**< Offset from TPU Base Address: 0x0x0C0 */ +#define MXC_R_TPU_MAA_MAWS ((uint32_t)0x000000D0UL) /**< Offset from TPU Base Address: 0x0x0D0 */ + /**@} end of group tpu_registers */ + +/** + * @ingroup tpu_registers + * @defgroup CTRL_Register + * @brief Crypto Control Register. + * @{ + */ +#define MXC_F_TPU_CTRL_RST_POS 0 /**< CTRL_RST Position */ +#define MXC_F_TPU_CTRL_RST ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_RST_POS)) /**< CTRL_RST Mask */ + +#define MXC_F_TPU_CTRL_INTR_POS 1 /**< CTRL_INTR Position */ +#define MXC_F_TPU_CTRL_INTR ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_INTR_POS)) /**< CTRL_INTR Mask */ + +#define MXC_F_TPU_CTRL_SRC_POS 2 /**< CTRL_SRC Position */ +#define MXC_F_TPU_CTRL_SRC ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_SRC_POS)) /**< CTRL_SRC Mask */ + +#define MXC_F_TPU_CTRL_BSO_POS 4 /**< CTRL_BSO Position */ +#define MXC_F_TPU_CTRL_BSO ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_BSO_POS)) /**< CTRL_BSO Mask */ + +#define MXC_F_TPU_CTRL_BSI_POS 5 /**< CTRL_BSI Position */ +#define MXC_F_TPU_CTRL_BSI ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_BSI_POS)) /**< CTRL_BSI Mask */ + +#define MXC_F_TPU_CTRL_WAIT_EN_POS 6 /**< CTRL_WAIT_EN Position */ +#define MXC_F_TPU_CTRL_WAIT_EN ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_WAIT_EN_POS)) /**< CTRL_WAIT_EN Mask */ + +#define MXC_F_TPU_CTRL_WAIT_POL_POS 7 /**< CTRL_WAIT_POL Position */ +#define MXC_F_TPU_CTRL_WAIT_POL ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_WAIT_POL_POS)) /**< CTRL_WAIT_POL Mask */ + +#define MXC_F_TPU_CTRL_WRSRC_POS 8 /**< CTRL_WRSRC Position */ +#define MXC_F_TPU_CTRL_WRSRC ((uint32_t)(0x3UL << MXC_F_TPU_CTRL_WRSRC_POS)) /**< CTRL_WRSRC Mask */ +#define MXC_V_TPU_CTRL_WRSRC_NONE ((uint32_t)0x0UL) /**< CTRL_WRSRC_NONE Value */ +#define MXC_S_TPU_CTRL_WRSRC_NONE \ + (MXC_V_TPU_CTRL_WRSRC_NONE << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_NONE Setting */ +#define MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT ((uint32_t)0x1UL) /**< CTRL_WRSRC_CIPHEROUTPUT Value */ +#define MXC_S_TPU_CTRL_WRSRC_CIPHEROUTPUT \ + (MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_CIPHEROUTPUT Setting */ +#define MXC_V_TPU_CTRL_WRSRC_READFIFO ((uint32_t)0x2UL) /**< CTRL_WRSRC_READFIFO Value */ +#define MXC_S_TPU_CTRL_WRSRC_READFIFO \ + (MXC_V_TPU_CTRL_WRSRC_READFIFO << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_READFIFO Setting */ +#define MXC_V_TPU_CTRL_WRSRC_RFU ((uint32_t)0x3UL) /**< CTRL_WRSRC_RFU Value */ +#define MXC_S_TPU_CTRL_WRSRC_RFU (MXC_V_TPU_CTRL_WRSRC_RFU << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_RFU Setting */ + +#define MXC_F_TPU_CTRL_RDSRC_POS 10 /**< CTRL_RDSRC Position */ +#define MXC_F_TPU_CTRL_RDSRC ((uint32_t)(0x3UL << MXC_F_TPU_CTRL_RDSRC_POS)) /**< CTRL_RDSRC Mask */ +#define MXC_V_TPU_CTRL_RDSRC_DMADISABLED ((uint32_t)0x0UL) /**< CTRL_RDSRC_DMADISABLED Value */ +#define MXC_S_TPU_CTRL_RDSRC_DMADISABLED \ + (MXC_V_TPU_CTRL_RDSRC_DMADISABLED << MXC_F_TPU_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMADISABLED Setting */ +#define MXC_V_TPU_CTRL_RDSRC_DMAORAPB ((uint32_t)0x1UL) /**< CTRL_RDSRC_DMAORAPB Value */ +#define MXC_S_TPU_CTRL_RDSRC_DMAORAPB \ + (MXC_V_TPU_CTRL_RDSRC_DMAORAPB << MXC_F_TPU_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMAORAPB Setting */ +#define MXC_V_TPU_CTRL_RDSRC_RNG ((uint32_t)0x2UL) /**< CTRL_RDSRC_RNG Value */ +#define MXC_S_TPU_CTRL_RDSRC_RNG (MXC_V_TPU_CTRL_RDSRC_RNG << MXC_F_TPU_CTRL_RDSRC_POS) /**< CTRL_RDSRC_RNG Setting */ + +#define MXC_F_TPU_CTRL_FLAG_MODE_POS 14 /**< CTRL_FLAG_MODE Position */ +#define MXC_F_TPU_CTRL_FLAG_MODE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_FLAG_MODE_POS)) /**< CTRL_FLAG_MODE Mask */ + +#define MXC_F_TPU_CTRL_DMADNEMSK_POS 15 /**< CTRL_DMADNEMSK Position */ +#define MXC_F_TPU_CTRL_DMADNEMSK ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DMADNEMSK_POS)) /**< CTRL_DMADNEMSK Mask */ + +#define MXC_F_TPU_CTRL_DMA_DONE_POS 24 /**< CTRL_DMA_DONE Position */ +#define MXC_F_TPU_CTRL_DMA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DMA_DONE_POS)) /**< CTRL_DMA_DONE Mask */ + +#define MXC_F_TPU_CTRL_GLS_DONE_POS 25 /**< CTRL_GLS_DONE Position */ +#define MXC_F_TPU_CTRL_GLS_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_GLS_DONE_POS)) /**< CTRL_GLS_DONE Mask */ + +#define MXC_F_TPU_CTRL_HSH_DONE_POS 26 /**< CTRL_HSH_DONE Position */ +#define MXC_F_TPU_CTRL_HSH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_HSH_DONE_POS)) /**< CTRL_HSH_DONE Mask */ + +#define MXC_F_TPU_CTRL_CPH_DONE_POS 27 /**< CTRL_CPH_DONE Position */ +#define MXC_F_TPU_CTRL_CPH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_CPH_DONE_POS)) /**< CTRL_CPH_DONE Mask */ + +#define MXC_F_TPU_CTRL_MAA_DONE_POS 28 /**< CTRL_MAA_DONE Position */ +#define MXC_F_TPU_CTRL_MAA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_MAA_DONE_POS)) /**< CTRL_MAA_DONE Mask */ + +#define MXC_F_TPU_CTRL_ERR_POS 29 /**< CTRL_ERR Position */ +#define MXC_F_TPU_CTRL_ERR ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_ERR_POS)) /**< CTRL_ERR Mask */ + +#define MXC_F_TPU_CTRL_RDY_POS 30 /**< CTRL_RDY Position */ +#define MXC_F_TPU_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ + +#define MXC_F_TPU_CTRL_DONE_POS 31 /**< CTRL_DONE Position */ +#define MXC_F_TPU_CTRL_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DONE_POS)) /**< CTRL_DONE Mask */ + +/**@} end of group CTRL_Register */ + +/** + * @ingroup tpu_registers + * @defgroup CIPHER_CTRL_Register + * @brief Cipher Control Register. + * @{ + */ +#define MXC_F_TPU_CIPHER_CTRL_ENC_POS 0 /**< CIPHER_CTRL_ENC Position */ +#define MXC_F_TPU_CIPHER_CTRL_ENC ((uint32_t)(0x1UL << MXC_F_TPU_CIPHER_CTRL_ENC_POS)) /**< CIPHER_CTRL_ENC Mask */ + +#define MXC_F_TPU_CIPHER_CTRL_KEY_POS 1 /**< CIPHER_CTRL_KEY Position */ +#define MXC_F_TPU_CIPHER_CTRL_KEY ((uint32_t)(0x1UL << MXC_F_TPU_CIPHER_CTRL_KEY_POS)) /**< CIPHER_CTRL_KEY Mask */ + +#define MXC_F_TPU_CIPHER_CTRL_SRC_POS 2 /**< CIPHER_CTRL_SRC Position */ +#define MXC_F_TPU_CIPHER_CTRL_SRC ((uint32_t)(0x3UL << MXC_F_TPU_CIPHER_CTRL_SRC_POS)) /**< CIPHER_CTRL_SRC Mask */ +#define MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY ((uint32_t)0x0UL) /**< CIPHER_CTRL_SRC_CIPHERKEY Value */ +#define MXC_S_TPU_CIPHER_CTRL_SRC_CIPHERKEY \ + (MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_CIPHERKEY Setting */ +#define MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE ((uint32_t)0x2UL) /**< CIPHER_CTRL_SRC_REGFILE Value */ +#define MXC_S_TPU_CIPHER_CTRL_SRC_REGFILE \ + (MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_REGFILE Setting */ +#define MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE ((uint32_t)0x3UL) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Value */ +#define MXC_S_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE \ + (MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE \ + << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Setting */ + +#define MXC_F_TPU_CIPHER_CTRL_CIPHER_POS 4 /**< CIPHER_CTRL_CIPHER Position */ +#define MXC_F_TPU_CIPHER_CTRL_CIPHER \ + ((uint32_t)(0x7UL << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS)) /**< CIPHER_CTRL_CIPHER Mask */ +#define MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS ((uint32_t)0x0UL) /**< CIPHER_CTRL_CIPHER_DIS Value */ +#define MXC_S_TPU_CIPHER_CTRL_CIPHER_DIS \ + (MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DIS Setting */ +#define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 ((uint32_t)0x1UL) /**< CIPHER_CTRL_CIPHER_AES128 Value */ +#define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES128 \ + (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES128 Setting \ + */ +#define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 ((uint32_t)0x2UL) /**< CIPHER_CTRL_CIPHER_AES192 Value */ +#define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES192 \ + (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES192 Setting \ + */ +#define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 ((uint32_t)0x3UL) /**< CIPHER_CTRL_CIPHER_AES256 Value */ +#define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES256 \ + (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES256 Setting \ + */ +#define MXC_V_TPU_CIPHER_CTRL_CIPHER_DES ((uint32_t)0x4UL) /**< CIPHER_CTRL_CIPHER_DES Value */ +#define MXC_S_TPU_CIPHER_CTRL_CIPHER_DES \ + (MXC_V_TPU_CIPHER_CTRL_CIPHER_DES << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DES Setting */ +#define MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES ((uint32_t)0x5UL) /**< CIPHER_CTRL_CIPHER_TDES Value */ +#define MXC_S_TPU_CIPHER_CTRL_CIPHER_TDES \ + (MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_TDES Setting */ + +#define MXC_F_TPU_CIPHER_CTRL_MODE_POS 8 /**< CIPHER_CTRL_MODE Position */ +#define MXC_F_TPU_CIPHER_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_TPU_CIPHER_CTRL_MODE_POS)) /**< CIPHER_CTRL_MODE Mask */ +#define MXC_V_TPU_CIPHER_CTRL_MODE_ECB ((uint32_t)0x0UL) /**< CIPHER_CTRL_MODE_ECB Value */ +#define MXC_S_TPU_CIPHER_CTRL_MODE_ECB \ + (MXC_V_TPU_CIPHER_CTRL_MODE_ECB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_ECB Setting */ +#define MXC_V_TPU_CIPHER_CTRL_MODE_CBC ((uint32_t)0x1UL) /**< CIPHER_CTRL_MODE_CBC Value */ +#define MXC_S_TPU_CIPHER_CTRL_MODE_CBC \ + (MXC_V_TPU_CIPHER_CTRL_MODE_CBC << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CBC Setting */ +#define MXC_V_TPU_CIPHER_CTRL_MODE_CFB ((uint32_t)0x2UL) /**< CIPHER_CTRL_MODE_CFB Value */ +#define MXC_S_TPU_CIPHER_CTRL_MODE_CFB \ + (MXC_V_TPU_CIPHER_CTRL_MODE_CFB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CFB Setting */ +#define MXC_V_TPU_CIPHER_CTRL_MODE_OFB ((uint32_t)0x3UL) /**< CIPHER_CTRL_MODE_OFB Value */ +#define MXC_S_TPU_CIPHER_CTRL_MODE_OFB \ + (MXC_V_TPU_CIPHER_CTRL_MODE_OFB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_OFB Setting */ +#define MXC_V_TPU_CIPHER_CTRL_MODE_CTR ((uint32_t)0x4UL) /**< CIPHER_CTRL_MODE_CTR Value */ +#define MXC_S_TPU_CIPHER_CTRL_MODE_CTR \ + (MXC_V_TPU_CIPHER_CTRL_MODE_CTR << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CTR Setting */ + +/**@} end of group CIPHER_CTRL_Register */ + +/** + * @ingroup tpu_registers + * @defgroup HASH_CTRL_Register + * @brief HASH Control Register. + * @{ + */ +#define MXC_F_TPU_HASH_CTRL_INIT_POS 0 /**< HASH_CTRL_INIT Position */ +#define MXC_F_TPU_HASH_CTRL_INIT ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_INIT_POS)) /**< HASH_CTRL_INIT Mask */ + +#define MXC_F_TPU_HASH_CTRL_XOR_POS 1 /**< HASH_CTRL_XOR Position */ +#define MXC_F_TPU_HASH_CTRL_XOR ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_XOR_POS)) /**< HASH_CTRL_XOR Mask */ + +#define MXC_F_TPU_HASH_CTRL_HASH_POS 2 /**< HASH_CTRL_HASH Position */ +#define MXC_F_TPU_HASH_CTRL_HASH ((uint32_t)(0x7UL << MXC_F_TPU_HASH_CTRL_HASH_POS)) /**< HASH_CTRL_HASH Mask */ +#define MXC_V_TPU_HASH_CTRL_HASH_DIS ((uint32_t)0x0UL) /**< HASH_CTRL_HASH_DIS Value */ +#define MXC_S_TPU_HASH_CTRL_HASH_DIS \ + (MXC_V_TPU_HASH_CTRL_HASH_DIS << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_DIS Setting */ +#define MXC_V_TPU_HASH_CTRL_HASH_SHA1 ((uint32_t)0x1UL) /**< HASH_CTRL_HASH_SHA1 Value */ +#define MXC_S_TPU_HASH_CTRL_HASH_SHA1 \ + (MXC_V_TPU_HASH_CTRL_HASH_SHA1 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA1 Setting */ +#define MXC_V_TPU_HASH_CTRL_HASH_SHA224 ((uint32_t)0x2UL) /**< HASH_CTRL_HASH_SHA224 Value */ +#define MXC_S_TPU_HASH_CTRL_HASH_SHA224 \ + (MXC_V_TPU_HASH_CTRL_HASH_SHA224 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA224 Setting */ +#define MXC_V_TPU_HASH_CTRL_HASH_SHA256 ((uint32_t)0x3UL) /**< HASH_CTRL_HASH_SHA256 Value */ +#define MXC_S_TPU_HASH_CTRL_HASH_SHA256 \ + (MXC_V_TPU_HASH_CTRL_HASH_SHA256 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA256 Setting */ +#define MXC_V_TPU_HASH_CTRL_HASH_SHA384 ((uint32_t)0x4UL) /**< HASH_CTRL_HASH_SHA384 Value */ +#define MXC_S_TPU_HASH_CTRL_HASH_SHA384 \ + (MXC_V_TPU_HASH_CTRL_HASH_SHA384 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA384 Setting */ +#define MXC_V_TPU_HASH_CTRL_HASH_SHA512 ((uint32_t)0x5UL) /**< HASH_CTRL_HASH_SHA512 Value */ +#define MXC_S_TPU_HASH_CTRL_HASH_SHA512 \ + (MXC_V_TPU_HASH_CTRL_HASH_SHA512 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA512 Setting */ + +#define MXC_F_TPU_HASH_CTRL_LAST_POS 5 /**< HASH_CTRL_LAST Position */ +#define MXC_F_TPU_HASH_CTRL_LAST ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_LAST_POS)) /**< HASH_CTRL_LAST Mask */ + +/**@} end of group HASH_CTRL_Register */ + +/** + * @ingroup tpu_registers + * @defgroup CRC_CTRL_Register + * @brief CRC Control Register. + * @{ + */ +#define MXC_F_TPU_CRC_CTRL_CRC_POS 0 /**< CRC_CTRL_CRC Position */ +#define MXC_F_TPU_CRC_CTRL_CRC ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_CRC_POS)) /**< CRC_CTRL_CRC Mask */ + +#define MXC_F_TPU_CRC_CTRL_MSB_POS 1 /**< CRC_CTRL_MSB Position */ +#define MXC_F_TPU_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_MSB_POS)) /**< CRC_CTRL_MSB Mask */ + +#define MXC_F_TPU_CRC_CTRL_PRNG_POS 2 /**< CRC_CTRL_PRNG Position */ +#define MXC_F_TPU_CRC_CTRL_PRNG ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_PRNG_POS)) /**< CRC_CTRL_PRNG Mask */ + +#define MXC_F_TPU_CRC_CTRL_ENT_POS 3 /**< CRC_CTRL_ENT Position */ +#define MXC_F_TPU_CRC_CTRL_ENT ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_ENT_POS)) /**< CRC_CTRL_ENT Mask */ + +#define MXC_F_TPU_CRC_CTRL_HAM_POS 4 /**< CRC_CTRL_HAM Position */ +#define MXC_F_TPU_CRC_CTRL_HAM ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_HAM_POS)) /**< CRC_CTRL_HAM Mask */ + +#define MXC_F_TPU_CRC_CTRL_HRST_POS 5 /**< CRC_CTRL_HRST Position */ +#define MXC_F_TPU_CRC_CTRL_HRST ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_HRST_POS)) /**< CRC_CTRL_HRST Mask */ + +/**@} end of group CRC_CTRL_Register */ + +/** + * @ingroup tpu_registers + * @defgroup DMA_SRC_Register + * @brief Crypto DMA Source Address. + * @{ + */ +#define MXC_F_TPU_DMA_SRC_ADDR_POS 0 /**< DMA_SRC_ADDR Position */ +#define MXC_F_TPU_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_SRC_ADDR_POS)) /**< DMA_SRC_ADDR Mask */ + +/**@} end of group DMA_SRC_Register */ + +/** + * @ingroup tpu_registers + * @defgroup DMA_DEST_Register + * @brief Crypto DMA Destination Address. + * @{ + */ +#define MXC_F_TPU_DMA_DEST_ADDR_POS 0 /**< DMA_DEST_ADDR Position */ +#define MXC_F_TPU_DMA_DEST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_DEST_ADDR_POS)) /**< DMA_DEST_ADDR Mask */ + +/**@} end of group DMA_DEST_Register */ + +/** + * @ingroup tpu_registers + * @defgroup DMA_CNT_Register + * @brief Crypto DMA Byte Count. + * @{ + */ +#define MXC_F_TPU_DMA_CNT_ADDR_POS 0 /**< DMA_CNT_ADDR Position */ +#define MXC_F_TPU_DMA_CNT_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_CNT_ADDR_POS)) /**< DMA_CNT_ADDR Mask */ + +/**@} end of group DMA_CNT_Register */ + +/** + * @ingroup tpu_registers + * @defgroup MAA_CTRL_Register + * @brief MAA Control Register. + * @{ + */ +#define MXC_F_TPU_MAA_CTRL_STC_POS 0 /**< MAA_CTRL_STC Position */ +#define MXC_F_TPU_MAA_CTRL_STC ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_STC_POS)) /**< MAA_CTRL_STC Mask */ + +#define MXC_F_TPU_MAA_CTRL_CLC_POS 1 /**< MAA_CTRL_CLC Position */ +#define MXC_F_TPU_MAA_CTRL_CLC ((uint32_t)(0x7UL << MXC_F_TPU_MAA_CTRL_CLC_POS)) /**< MAA_CTRL_CLC Mask */ +#define MXC_V_TPU_MAA_CTRL_CLC_EXP ((uint32_t)0x0UL) /**< MAA_CTRL_CLC_EXP Value */ +#define MXC_S_TPU_MAA_CTRL_CLC_EXP \ + (MXC_V_TPU_MAA_CTRL_CLC_EXP << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_EXP Setting */ +#define MXC_V_TPU_MAA_CTRL_CLC_SQ ((uint32_t)0x1UL) /**< MAA_CTRL_CLC_SQ Value */ +#define MXC_S_TPU_MAA_CTRL_CLC_SQ \ + (MXC_V_TPU_MAA_CTRL_CLC_SQ << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SQ Setting */ +#define MXC_V_TPU_MAA_CTRL_CLC_MUL ((uint32_t)0x2UL) /**< MAA_CTRL_CLC_MUL Value */ +#define MXC_S_TPU_MAA_CTRL_CLC_MUL \ + (MXC_V_TPU_MAA_CTRL_CLC_MUL << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_MUL Setting */ +#define MXC_V_TPU_MAA_CTRL_CLC_SQMUL ((uint32_t)0x3UL) /**< MAA_CTRL_CLC_SQMUL Value */ +#define MXC_S_TPU_MAA_CTRL_CLC_SQMUL \ + (MXC_V_TPU_MAA_CTRL_CLC_SQMUL << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SQMUL Setting */ +#define MXC_V_TPU_MAA_CTRL_CLC_ADD ((uint32_t)0x4UL) /**< MAA_CTRL_CLC_ADD Value */ +#define MXC_S_TPU_MAA_CTRL_CLC_ADD \ + (MXC_V_TPU_MAA_CTRL_CLC_ADD << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_ADD Setting */ +#define MXC_V_TPU_MAA_CTRL_CLC_SUB ((uint32_t)0x5UL) /**< MAA_CTRL_CLC_SUB Value */ +#define MXC_S_TPU_MAA_CTRL_CLC_SUB \ + (MXC_V_TPU_MAA_CTRL_CLC_SUB << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SUB Setting */ + +#define MXC_F_TPU_MAA_CTRL_OCALC_POS 4 /**< MAA_CTRL_OCALC Position */ +#define MXC_F_TPU_MAA_CTRL_OCALC ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_OCALC_POS)) /**< MAA_CTRL_OCALC Mask */ + +#define MXC_F_TPU_MAA_CTRL_MAAER_POS 7 /**< MAA_CTRL_MAAER Position */ +#define MXC_F_TPU_MAA_CTRL_MAAER ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_MAAER_POS)) /**< MAA_CTRL_MAAER Mask */ + +#define MXC_F_TPU_MAA_CTRL_AMS_POS 8 /**< MAA_CTRL_AMS Position */ +#define MXC_F_TPU_MAA_CTRL_AMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_AMS_POS)) /**< MAA_CTRL_AMS Mask */ + +#define MXC_F_TPU_MAA_CTRL_BMS_POS 10 /**< MAA_CTRL_BMS Position */ +#define MXC_F_TPU_MAA_CTRL_BMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_BMS_POS)) /**< MAA_CTRL_BMS Mask */ + +#define MXC_F_TPU_MAA_CTRL_EMS_POS 12 /**< MAA_CTRL_EMS Position */ +#define MXC_F_TPU_MAA_CTRL_EMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_EMS_POS)) /**< MAA_CTRL_EMS Mask */ + +#define MXC_F_TPU_MAA_CTRL_MMS_POS 14 /**< MAA_CTRL_MMS Position */ +#define MXC_F_TPU_MAA_CTRL_MMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_MMS_POS)) /**< MAA_CTRL_MMS Mask */ + +#define MXC_F_TPU_MAA_CTRL_AMA_POS 16 /**< MAA_CTRL_AMA Position */ +#define MXC_F_TPU_MAA_CTRL_AMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_AMA_POS)) /**< MAA_CTRL_AMA Mask */ + +#define MXC_F_TPU_MAA_CTRL_BMA_POS 20 /**< MAA_CTRL_BMA Position */ +#define MXC_F_TPU_MAA_CTRL_BMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_BMA_POS)) /**< MAA_CTRL_BMA Mask */ + +#define MXC_F_TPU_MAA_CTRL_RMA_POS 24 /**< MAA_CTRL_RMA Position */ +#define MXC_F_TPU_MAA_CTRL_RMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_RMA_POS)) /**< MAA_CTRL_RMA Mask */ + +#define MXC_F_TPU_MAA_CTRL_TMA_POS 28 /**< MAA_CTRL_TMA Position */ +#define MXC_F_TPU_MAA_CTRL_TMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_TMA_POS)) /**< MAA_CTRL_TMA Mask */ + +/**@} end of group MAA_CTRL_Register */ + +/** + * @ingroup tpu_registers + * @defgroup DIN_Register + * @brief Crypto Data Input. Data input can be written to this register instead of using + * the DMA. This register writes to the FIFO. This register occupies four + * successive words to allow the use of multi-store instructions. Words can be + * written to any location, they will be placed in the FIFO in the order they are + * written. The endian swap input control bit affects this register. + * @{ + */ +#define MXC_F_TPU_DIN_DATA_POS 0 /**< DIN_DATA Position */ +#define MXC_F_TPU_DIN_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DIN_DATA_POS)) /**< DIN_DATA Mask */ + +/**@} end of group DIN_Register */ + +/** + * @ingroup tpu_registers + * @defgroup DOUT_Register + * @brief Crypto Data Output. Resulting data from cipher calculation. Data is placed in + * the lower words of these four registers depending on the algorithm. For block + * cipher modes, this register holds the result of most recent encryption or + * decryption operation. These registers are affected by the endian swap bits. + * @{ + */ +#define MXC_F_TPU_DOUT_DATA_POS 0 /**< DOUT_DATA Position */ +#define MXC_F_TPU_DOUT_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DOUT_DATA_POS)) /**< DOUT_DATA Mask */ + +/**@} end of group DOUT_Register */ + +/** + * @ingroup tpu_registers + * @defgroup CRC_POLY_Register + * @brief CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or + * LFSR) should be written to this register. This register is affected by the MSB + * control bit. + * @{ + */ +#define MXC_F_TPU_CRC_POLY_POLY_POS 0 /**< CRC_POLY_POLY Position */ +#define MXC_F_TPU_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_POLY_POLY_POS)) /**< CRC_POLY_POLY Mask */ + +/**@} end of group CRC_POLY_Register */ + +/** + * @ingroup tpu_registers + * @defgroup CRC_VAL_Register + * @brief CRC Value. This is the state for the Galois Field. This register holds the + * result of a CRC calculation or the current state of the LFSR. This register is + * affected by the MSB control bit. + * @{ + */ +#define MXC_F_TPU_CRC_VAL_VAL_POS 0 /**< CRC_VAL_VAL Position */ +#define MXC_F_TPU_CRC_VAL_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_VAL_VAL_POS)) /**< CRC_VAL_VAL Mask */ + +/**@} end of group CRC_VAL_Register */ + +/** + * @ingroup tpu_registers + * @defgroup CRC_PRNG_Register + * @brief Pseudo Random Value. Output of the Galois Field shift register. This holds the + * resulting pseudo-random number if entropy is disabled or true random number if + * entropy is enabled. + * @{ + */ +#define MXC_F_TPU_CRC_PRNG_PRNG_POS 0 /**< CRC_PRNG_PRNG Position */ +#define MXC_F_TPU_CRC_PRNG_PRNG ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_PRNG_PRNG_POS)) /**< CRC_PRNG_PRNG Mask */ + +/**@} end of group CRC_PRNG_Register */ + +/** + * @ingroup tpu_registers + * @defgroup HAM_ECC_Register + * @brief Hamming ECC Register. + * @{ + */ +#define MXC_F_TPU_HAM_ECC_ECC_POS 0 /**< HAM_ECC_ECC Position */ +#define MXC_F_TPU_HAM_ECC_ECC ((uint32_t)(0xFFFFUL << MXC_F_TPU_HAM_ECC_ECC_POS)) /**< HAM_ECC_ECC Mask */ + +#define MXC_F_TPU_HAM_ECC_PAR_POS 16 /**< HAM_ECC_PAR Position */ +#define MXC_F_TPU_HAM_ECC_PAR ((uint32_t)(0x1UL << MXC_F_TPU_HAM_ECC_PAR_POS)) /**< HAM_ECC_PAR Mask */ + +/**@} end of group HAM_ECC_Register */ + +/** + * @ingroup tpu_registers + * @defgroup CIPHER_INIT_Register + * @brief Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR + * modes, this register holds the initial value. This register is updated with each + * encryption or decryption operation. This register is affected by the endian swap + * bits. + * @{ + */ +#define MXC_F_TPU_CIPHER_INIT_IVEC_POS 0 /**< CIPHER_INIT_IVEC Position */ +#define MXC_F_TPU_CIPHER_INIT_IVEC \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CIPHER_INIT_IVEC_POS)) /**< CIPHER_INIT_IVEC Mask */ + +/**@} end of group CIPHER_INIT_Register */ + +/** + * @ingroup tpu_registers + * @defgroup CIPHER_KEY_Register + * @brief Cipher Key. This register holds the key used for block cipher operations. The + * lower words are used for block ciphers that use shorter key lengths. This + * register is affected by the endian swap input control bits. + * @{ + */ +#define MXC_F_TPU_CIPHER_KEY_KEY_POS 0 /**< CIPHER_KEY_KEY Position */ +#define MXC_F_TPU_CIPHER_KEY_KEY \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CIPHER_KEY_KEY_POS)) /**< CIPHER_KEY_KEY Mask \ + */ + +/**@} end of group CIPHER_KEY_Register */ + +/** + * @ingroup tpu_registers + * @defgroup HASH_DIGEST_Register + * @brief This register holds the calculated hash value. This register is affected by the + * endian swap bits. + * @{ + */ +#define MXC_F_TPU_HASH_DIGEST_HASH_POS 0 /**< HASH_DIGEST_HASH Position */ +#define MXC_F_TPU_HASH_DIGEST_HASH \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_HASH_DIGEST_HASH_POS)) /**< HASH_DIGEST_HASH Mask */ + +/**@} end of group HASH_DIGEST_Register */ + +/** + * @ingroup tpu_registers + * @defgroup HASH_MSG_SZ_Register + * @brief Message Size. This register holds the lowest 32-bit of message size in bytes. + * @{ + */ +#define MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS 0 /**< HASH_MSG_SZ_MSGSZ Position */ +#define MXC_F_TPU_HASH_MSG_SZ_MSGSZ \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS)) /**< HASH_MSG_SZ_MSGSZ Mask */ + +/**@} end of group HASH_MSG_SZ_Register */ + +/** + * @ingroup tpu_registers + * @defgroup MAA_MAWS_Register + * @brief MAA Word Size. This register defines the number of bits for a modular operation. + * This register must be set to a valid value prior to the MAA operation start. + * Valid values are from 1 to 2048. Invalid values are ignored and will not + * initiate a MAA operation. + * @{ + */ +#define MXC_F_TPU_MAA_MAWS_MAWS_POS 0 /**< MAA_MAWS_MAWS Position */ +#define MXC_F_TPU_MAA_MAWS_MAWS ((uint32_t)(0xFFFUL << MXC_F_TPU_MAA_MAWS_MAWS_POS)) /**< MAA_MAWS_MAWS Mask */ + +/**@} end of group MAA_MAWS_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _TPU_REGS_H_ */ diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c index 267fd4312..ed6083441 100644 --- a/src/flash/nor/max32xxx.c +++ b/src/flash/nor/max32xxx.c @@ -2,7 +2,7 @@ /*************************************************************************** * Copyright (C) 2016 by Maxim Integrated * - * Kevin Gillespie * + * Copyright (C) 2025 Analog Devices, Inc. * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -13,90 +13,112 @@ #include #include #include +#include +#include -/* Register Addresses */ -#define FLSH_ADDR 0x000 -#define FLSH_CLKDIV 0x004 -#define FLSH_CN 0x008 -#define PR1E_ADDR 0x00C -#define PR2S_ADDR 0x010 -#define PR2E_ADDR 0x014 -#define PR3S_ADDR 0x018 -#define PR3E_ADDR 0x01C -#define FLSH_MD 0x020 -#define FLSH_INT 0x024 -#define FLSH_DATA0 0x030 -#define FLSH_DATA1 0x034 -#define FLSH_DATA2 0x038 -#define FLSH_DATA3 0x03C -#define FLSH_BL_CTRL 0x170 -#define FLSH_PROT 0x300 +// Register addresses +#define FLC_ADDR 0x00000000 +#define FLC_CLKDIV 0x00000004 +#define FLC_CN 0x00000008 +#define FLC_PR1E_ADDR 0x0000000C +#define FLC_PR2S_ADDR 0x00000010 +#define FLC_PR2E_ADDR 0x00000014 +#define FLC_PR3S_ADDR 0x00000018 +#define FLC_PR3E_ADDR 0x0000001C +#define FLC_MD 0x00000020 +#define FLC_INT 0x00000024 +#define FLC_DATA0 0x00000030 +#define FLC_DATA1 0x00000034 +#define FLC_DATA2 0x00000038 +#define FLC_DATA3 0x0000003C +#define FLC_BL_CTRL 0x00000170 +#define FLC_PROT 0x00000300 -#define ARM_PID_REG 0xE00FFFE0 -#define MAX326XX_ID_REG 0x40000838 +#define ARM_PID_REG 0xE00FFFE0 +#define MAX326XX_ID_REG 0x40000838 -/* Register settings */ -#define FLSH_INT_AF 0x00000002 +// Register settings +#define FLC_INT_AF 0x00000002 -#define FLSH_CN_UNLOCK_MASK 0xF0000000 -#define FLSH_CN_UNLOCK_VALUE 0x20000000 +#define FLC_CN_UNLOCK_MASK 0xF0000000 +#define FLC_CN_UNLOCK_VALUE 0x20000000 -#define FLSH_CN_PEND 0x01000000 +#define FLC_CN_PEND 0x01000000 +#define FLC_CN_ERASE_CODE_MASK 0x0000FF00 +#define FLC_CN_ERASE_CODE_PGE 0x00005500 +#define FLC_CN_ERASE_CODE_ME 0x0000AA00 +#define FLC_CN_32BIT 0x00000010 +#define FLC_CN_PGE 0x00000004 +#define FLC_CN_ME 0x00000002 +#define FLC_CN_WR 0x00000001 +#define FLC_CN_PGE 0x00000004 +#define FLC_CN_ME 0x00000002 +#define FLC_CN_WR 0x00000001 -#define FLSH_CN_ERASE_CODE_MASK 0x0000FF00 -#define FLSH_CN_ERASE_CODE_PGE 0x00005500 -#define FLSH_CN_ERASE_CODE_ME 0x0000AA00 +#define FLC_BL_CTRL_23 0x00020000 +#define FLC_BL_CTRL_IFREN 0x00000001 -#define FLSH_CN_PGE 0x00000004 -#define FLSH_CN_ME 0x00000002 -#define FLSH_CN_WR 0x00000001 -#define FLASH_BL_CTRL_23 0x00020000 -#define FLASH_BL_CTRL_IFREN 0x00000001 +#define MASK_FLASH_BUSY (0x048800E0 & ~0x04000000) +#define MASK_DISABLE_INTS (0xFFFFFCFC) +#define MASK_FLASH_UNLOCKED (0xF588FFEF & ~0x04000000) +#define MASK_FLASH_LOCK (0xF588FFEF & ~0x04000000) +#define MASK_FLASH_ERASE (0xF588FFEF & ~0x04000000) +#define MASK_FLASH_ERASED (0xF48800EB & ~0x04000000) +#define MASK_ACCESS_VIOLATIONS (0xFFFFFCFC) +#define MASK_FLASH_WRITE (0xF588FFEF & ~0x04000000) +#define MASK_WRITE_ALIGNED (0xF588FFEF & ~0x04000000) +#define MASK_WRITE_COMPLETE (0xF488FFEE & ~0x04000000) +#define MASK_WRITE_BURST (0xF588FFEF & ~0x04000000) +#define MASK_BURST_COMPLETE (0xF488FFEE & ~0x04000000) +#define MASK_WRITE_REMAINING (0xF588FFEF & ~0x04000000) +#define MASK_REMAINING_COMPLETE (0xF488FFEE & ~0x04000000) +#define MASK_MASS_ERASE (0xF588FFEF & ~0x04000000) +#define MASK_ERASE_COMPLETE (0xF48800ED & ~0x04000000) -#define ARM_PID_DEFAULT_CM3 0xB4C3 -#define ARM_PID_DEFAULT_CM4 0xB4C4 -#define MAX326XX_ID 0x4D +#define ARM_PID_DEFAULT_CM3 0x0000B4C3 +#define ARM_PID_DEFAULT_CM4 0x0000B4C4 +#define MAX326XX_ID 0x0000004D + +#define OPTIONS_128 0x01 // Perform 128 bit flash writes +#define OPTIONS_ENC 0x02 // Encrypt the flash contents +#define OPTIONS_AUTH 0x04 // Authenticate the flash contents +#define OPTIONS_COUNT 0x08 // Add counter values to authentication +#define OPTIONS_INTER 0x10 // Interleave the authentication and count values +#define OPTIONS_RELATIVE_XOR 0x20 // Only XOR the offset of the address when encrypting +#define OPTIONS_KEYSIZE 0x40 // Use a 256 bit KEY static int max32xxx_mass_erase(struct flash_bank *bank); struct max32xxx_flash_bank { bool probed; - int max326xx; + bool max326xx; unsigned int flash_size; unsigned int flc_base; unsigned int sector_size; unsigned int clkdiv_value; - uint32_t int_state; - unsigned int burst_size_bits; + unsigned int int_state; + unsigned int options; }; -/* see contrib/loaders/flash/max32xxx/max32xxx.s for src */ -static const uint8_t write_code[] = { -#include "../../../contrib/loaders/flash/max32xxx/max32xxx.inc" +static const uint8_t write_code_arm[] = { +#include "../../../contrib/loaders/flash/max32xxx/max32xxx_write_arm.inc" }; -/* Config Command: flash bank name driver base size chip_width bus_width target [driver_option] - flash bank max32xxx 0 0 [burst_bits] - */ FLASH_BANK_COMMAND_HANDLER(max32xxx_flash_bank_command) { struct max32xxx_flash_bank *info; - if (CMD_ARGC < 9) { - LOG_WARNING("incomplete flash bank max32xxx configuration: 0 0 [burst_bits]"); + if (CMD_ARGC != 10) { + LOG_ERROR("incorrect flash bank max32xxx configuration: 0 0 "); return ERROR_FLASH_BANK_INVALID; } - info = calloc(1, sizeof(struct max32xxx_flash_bank)); - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], info->flash_size); - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[6], info->flc_base); - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[7], info->sector_size); - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[8], info->clkdiv_value); - - if (CMD_ARGC > 9) - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[9], info->burst_size_bits); - else - info->burst_size_bits = 32; + info = calloc(sizeof(struct max32xxx_flash_bank), 1); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], info->flash_size); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], info->flc_base); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[7], info->sector_size); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[8], info->clkdiv_value); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[9], info->options); info->int_state = 0; bank->driver_priv = info; @@ -114,63 +136,67 @@ static int get_info(struct flash_bank *bank, struct command_invocation *cmd) return ERROR_OK; } -/*************************************************************************** -* flash operations -***************************************************************************/ +static bool max32xxx_flash_busy(uint32_t flash_cn) +{ + if (flash_cn & (FLC_CN_PGE | FLC_CN_ME | FLC_CN_WR)) + return true; + + return false; +} static int max32xxx_flash_op_pre(struct flash_bank *bank) { struct target *target = bank->target; struct max32xxx_flash_bank *info = bank->driver_priv; - uint32_t flsh_cn; + uint32_t flash_cn; uint32_t bootloader; - /* Check if the flash controller is busy */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - if (flsh_cn & (FLSH_CN_PEND | FLSH_CN_ERASE_CODE_MASK | FLSH_CN_PGE | - FLSH_CN_ME | FLSH_CN_WR)) + // Check if the flash controller is busy + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + if (max32xxx_flash_busy(flash_cn)) return ERROR_FLASH_BUSY; - /* Refresh flash controller timing */ - target_write_u32(target, info->flc_base + FLSH_CLKDIV, info->clkdiv_value); + // Refresh flash controller timing + target_write_u32(target, info->flc_base + FLC_CLKDIV, info->clkdiv_value); - /* Clear and disable flash programming interrupts */ - target_read_u32(target, info->flc_base + FLSH_INT, &info->int_state); - target_write_u32(target, info->flc_base + FLSH_INT, 0x00000000); + // Clear and disable flash programming interrupts + target_read_u32(target, info->flc_base + FLC_INT, &info->int_state); + target_write_u32(target, info->flc_base + FLC_INT, 0); - /* Clear the lower bit in the bootloader configuration register in case flash page 0 has been replaced */ - if (target_read_u32(target, info->flc_base + FLSH_BL_CTRL, &bootloader) != ERROR_OK) { - LOG_ERROR("Read failure on FLSH_BL_CTRL"); + /* Clear the lower bit in the bootloader configuration register in case flash page 0 has + * been replaced */ + if (target_read_u32(target, info->flc_base + FLC_BL_CTRL, &bootloader) != ERROR_OK) { + LOG_ERROR("Read failure on FLC_BL_CTRL"); return ERROR_FAIL; } - if (bootloader & FLASH_BL_CTRL_23) { - LOG_WARNING("FLSH_BL_CTRL indicates BL mode 2 or mode 3."); - if (bootloader & FLASH_BL_CTRL_IFREN) { + if (bootloader & FLC_BL_CTRL_23) { + LOG_WARNING("FLC_BL_CTRL indicates BL mode 2 or mode 3."); + if (bootloader & FLC_BL_CTRL_IFREN) { LOG_WARNING("Flash page 0 swapped out, attempting to swap back in for programming"); - bootloader &= ~(FLASH_BL_CTRL_IFREN); - if (target_write_u32(target, info->flc_base + FLSH_BL_CTRL, bootloader) != ERROR_OK) { - LOG_ERROR("Write failure on FLSH_BL_CTRL"); + bootloader &= ~(FLC_BL_CTRL_IFREN); + if (target_write_u32(target, info->flc_base + FLC_BL_CTRL, + bootloader) != ERROR_OK) { + LOG_ERROR("Write failure on FLC_BL_CTRL"); return ERROR_FAIL; } - if (target_read_u32(target, info->flc_base + FLSH_BL_CTRL, &bootloader) != ERROR_OK) { - LOG_ERROR("Read failure on FLSH_BL_CTRL"); + if (target_read_u32(target, info->flc_base + FLC_BL_CTRL, + &bootloader) != ERROR_OK) { + LOG_ERROR("Read failure on FLC_BL_CTRL"); return ERROR_FAIL; } - if (bootloader & FLASH_BL_CTRL_IFREN) { - /* Bummer */ + if (bootloader & FLC_BL_CTRL_IFREN) LOG_ERROR("Unable to swap flash page 0 back in. Writes to page 0 will fail."); - } } } - /* Unlock flash */ - flsh_cn &= ~FLSH_CN_UNLOCK_MASK; - flsh_cn |= FLSH_CN_UNLOCK_VALUE; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + // Unlock flash + flash_cn &= ~(FLC_CN_UNLOCK_MASK); + flash_cn |= FLC_CN_UNLOCK_VALUE; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); - /* Confirm flash is unlocked */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - if ((flsh_cn & FLSH_CN_UNLOCK_VALUE) != FLSH_CN_UNLOCK_VALUE) + // Confirm flash is unlocked + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + if ((flash_cn & FLC_CN_UNLOCK_VALUE) != FLC_CN_UNLOCK_VALUE) return ERROR_FAIL; return ERROR_OK; @@ -180,15 +206,15 @@ static int max32xxx_flash_op_post(struct flash_bank *bank) { struct target *target = bank->target; struct max32xxx_flash_bank *info = bank->driver_priv; - uint32_t flsh_cn; + uint32_t flash_cn; - /* Restore flash programming interrupts */ - target_write_u32(target, info->flc_base + FLSH_INT, info->int_state); + // Restore flash programming interrupts + target_write_u32(target, info->flc_base + FLC_INT, info->int_state); - /* Lock flash */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - flsh_cn &= ~FLSH_CN_UNLOCK_MASK; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + // Lock flash + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + flash_cn &= ~(FLC_CN_UNLOCK_MASK); + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); return ERROR_OK; } @@ -208,12 +234,12 @@ static int max32xxx_protect_check(struct flash_bank *bank) return ERROR_FLASH_OPER_UNSUPPORTED; } - /* Check the protection */ + // Check the protection for (unsigned int i = 0; i < bank->num_sectors; i++) { - if (i%32 == 0) - target_read_u32(target, info->flc_base + FLSH_PROT + ((i/32)*4), &temp_reg); + if (i % 32 == 0) + target_read_u32(target, info->flc_base + FLC_PROT + ((i / 32) * 4), &temp_reg); - if (temp_reg & (0x1 << i%32)) + if (temp_reg & (0x1 << i % 32)) bank->sectors[i].is_protected = 1; else bank->sectors[i].is_protected = 0; @@ -222,9 +248,9 @@ static int max32xxx_protect_check(struct flash_bank *bank) } static int max32xxx_erase(struct flash_bank *bank, unsigned int first, - unsigned int last) + unsigned int last) { - uint32_t flsh_cn, flsh_int; + uint32_t flash_cn, flash_int; struct max32xxx_flash_bank *info = bank->driver_priv; struct target *target = bank->target; int retval; @@ -238,13 +264,13 @@ static int max32xxx_erase(struct flash_bank *bank, unsigned int first, if (!info->probed) return ERROR_FLASH_BANK_NOT_PROBED; - if ((last < first) || (last >= bank->num_sectors)) + if (last < first || last >= bank->num_sectors) return ERROR_FLASH_SECTOR_INVALID; - if ((first == 0) && (last == (bank->num_sectors - 1))) + if (first == 0 && last == (bank->num_sectors - 1)) return max32xxx_mass_erase(bank); - /* Prepare to issue flash operation */ + // Prepare to issue flash operation retval = max32xxx_flash_op_pre(bank); if (retval != ERROR_OK) @@ -252,43 +278,43 @@ static int max32xxx_erase(struct flash_bank *bank, unsigned int first, int erased = 0; for (unsigned int banknr = first; banknr <= last; banknr++) { - - /* Check the protection */ + // Check the protection if (bank->sectors[banknr].is_protected == 1) { LOG_WARNING("Flash sector %u is protected", banknr); continue; - } else + } else { erased = 1; + } - /* Address is first word in page */ - target_write_u32(target, info->flc_base + FLSH_ADDR, banknr * info->sector_size); + // Address is first word in page + target_write_u32(target, info->flc_base + FLC_ADDR, banknr * info->sector_size); - /* Write page erase code */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - flsh_cn |= FLSH_CN_ERASE_CODE_PGE; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + // Write page erase code + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + flash_cn |= FLC_CN_ERASE_CODE_PGE; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); - /* Issue page erase command */ - flsh_cn |= 0x4; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + // Issue page erase command + flash_cn |= FLC_CN_PGE; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); - /* Wait until erase complete */ + // Wait until erase complete retry = 1000; do { - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - } while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND)); + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + } while ((--retry > 0) && max32xxx_flash_busy(flash_cn)); if (retry <= 0) { - LOG_ERROR("Timed out waiting for flash page erase @ 0x%08x", - banknr * info->sector_size); + LOG_ERROR("Timed out waiting for flash page erase @ 0x%08" PRIx32, + (banknr * info->sector_size)); return ERROR_FLASH_OPERATION_FAILED; } - /* Check access violations */ - target_read_u32(target, info->flc_base + FLSH_INT, &flsh_int); - if (flsh_int & FLSH_INT_AF) { + // Check access violations + target_read_u32(target, info->flc_base + FLC_INT, &flash_int); + if (flash_int & FLC_INT_AF) { LOG_ERROR("Error erasing flash page %i", banknr); - target_write_u32(target, info->flc_base + FLSH_INT, 0); + target_write_u32(target, info->flc_base + FLC_INT, 0); max32xxx_flash_op_post(bank); return ERROR_FLASH_OPERATION_FAILED; } @@ -307,7 +333,7 @@ static int max32xxx_erase(struct flash_bank *bank, unsigned int first, } static int max32xxx_protect(struct flash_bank *bank, int set, - unsigned int first, unsigned int last) + unsigned int first, unsigned int last) { struct max32xxx_flash_bank *info = bank->driver_priv; struct target *target = bank->target; @@ -324,22 +350,22 @@ static int max32xxx_protect(struct flash_bank *bank, int set, if (!info->max326xx) return ERROR_FLASH_OPER_UNSUPPORTED; - if ((last < first) || (last >= bank->num_sectors)) + if (last < first || last >= bank->num_sectors) return ERROR_FLASH_SECTOR_INVALID; - /* Setup the protection on the pages given */ + // Setup the protection on the pages given for (unsigned int page = first; page <= last; page++) { if (set) { - /* Set the write/erase bit for this page */ - target_read_u32(target, info->flc_base + FLSH_PROT + (page/32), &temp_reg); - temp_reg |= (0x1 << page%32); - target_write_u32(target, info->flc_base + FLSH_PROT + (page/32), temp_reg); + // Set the write/erase bit for this page + target_read_u32(target, info->flc_base + FLC_PROT + (page / 32), &temp_reg); + temp_reg |= (0x1 << page % 32); + target_write_u32(target, info->flc_base + FLC_PROT + (page / 32), temp_reg); bank->sectors[page].is_protected = 1; } else { - /* Clear the write/erase bit for this page */ - target_read_u32(target, info->flc_base + FLSH_PROT + (page/32), &temp_reg); - temp_reg &= ~(0x1 << page%32); - target_write_u32(target, info->flc_base + FLSH_PROT + (page/32), temp_reg); + // Clear the write/erase bit for this page + target_read_u32(target, info->flc_base + FLC_PROT + (page / 32), &temp_reg); + temp_reg &= ~(0x1 << page % 32); + target_write_u32(target, info->flc_base + FLC_PROT + (page / 32), temp_reg); bank->sectors[page].is_protected = 0; } } @@ -348,38 +374,41 @@ static int max32xxx_protect(struct flash_bank *bank, int set, } static int max32xxx_write_block(struct flash_bank *bank, const uint8_t *buffer, - uint32_t offset, uint32_t wcount) + uint32_t offset, uint32_t len) { struct max32xxx_flash_bank *info = bank->driver_priv; struct target *target = bank->target; + const char *target_type_name = (const char *)target->type->name; uint32_t buffer_size = 16384; struct working_area *source; struct working_area *write_algorithm; - uint32_t address = bank->base + offset; struct reg_param reg_params[5]; + struct mem_param mem_param[2]; struct armv7m_algorithm armv7m_info; int retval = ERROR_OK; - /* power of two, and multiple of word size */ + // power of two, and multiple of word size static const unsigned int buf_min = 128; + uint8_t *write_code; + int write_code_size; - /* for small buffers it's faster not to download an algorithm */ - if (wcount * 4 < buf_min) + + if (strcmp(target_type_name, "cortex_m") == 0) { + write_code = (uint8_t *)write_code_arm; + write_code_size = sizeof(write_code_arm); + } else { return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } - LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "", - bank, buffer, offset, wcount); + LOG_DEBUG("bank=%p buffer=%p offset=%08" PRIx32 " len=%08" PRIx32 "", + bank, buffer, offset, len); - /* flash write code */ - if (target_alloc_working_area(target, sizeof(write_code), &write_algorithm) != ERROR_OK) { + // flash write code + if (target_alloc_working_area(target, write_code_size, &write_algorithm) != ERROR_OK) { LOG_DEBUG("no working area for block memory writes"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - /* plus a buffer big enough for this data */ - if (wcount * 4 < buffer_size) - buffer_size = wcount * 4; - - /* memory buffer */ + // memory buffer while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) { buffer_size /= 2; @@ -392,24 +421,53 @@ static int max32xxx_write_block(struct flash_bank *bank, const uint8_t *buffer, target_name(target), buffer_size); } - target_write_buffer(target, write_algorithm->address, sizeof(write_code), + target_write_buffer(target, write_algorithm->address, write_code_size, write_code); armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; armv7m_info.core_mode = ARM_MODE_THREAD; - init_reg_param(®_params[0], "r0", 32, PARAM_OUT); - init_reg_param(®_params[1], "r1", 32, PARAM_OUT); - init_reg_param(®_params[2], "r2", 32, PARAM_OUT); - init_reg_param(®_params[3], "r3", 32, PARAM_OUT); - init_reg_param(®_params[4], "r4", 32, PARAM_OUT); + + // TODO: a0-a3 for RISCV + + if (strcmp(target_type_name, "cortex_m") == 0) { + init_reg_param(®_params[0], "r0", 32, PARAM_OUT); + init_reg_param(®_params[1], "r1", 32, PARAM_OUT); + init_reg_param(®_params[2], "r2", 32, PARAM_OUT); + init_reg_param(®_params[3], "r3", 32, PARAM_OUT); + } else { + init_reg_param(®_params[0], "a0", 32, PARAM_OUT); + init_reg_param(®_params[1], "a1", 32, PARAM_OUT); + init_reg_param(®_params[2], "a2", 32, PARAM_OUT); + init_reg_param(®_params[3], "a3", 32, PARAM_OUT); + } + init_reg_param(®_params[4], "sp", 32, PARAM_OUT); buf_set_u32(reg_params[0].value, 0, 32, source->address); buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size); - buf_set_u32(reg_params[2].value, 0, 32, address); - buf_set_u32(reg_params[3].value, 0, 32, wcount); - buf_set_u32(reg_params[4].value, 0, 32, info->flc_base); - retval = target_run_flash_async_algorithm(target, buffer, wcount, 4, 0, NULL, - 5, reg_params, source->address, source->size, write_algorithm->address, 0, &armv7m_info); + buf_set_u32(reg_params[2].value, 0, 32, len); + buf_set_u32(reg_params[3].value, 0, 32, offset); + buf_set_u32(reg_params[4].value, 0, 32, source->address + source->size); + + // mem_params for options + init_mem_param(&mem_param[0], source->address + (source->size - 8 - 128), 4, PARAM_OUT); + init_mem_param(&mem_param[1], source->address + (source->size - 4 - 128), 4, PARAM_OUT); + buf_set_u32(mem_param[0].value, 0, 32, info->options); + buf_set_u32(mem_param[1].value, 0, 32, info->flc_base); + + // leave room for stack, 32-bit options and encryption buffer + retval = target_run_flash_async_algorithm(target, + buffer, + len, + 1, + 2, + mem_param, + 5, + reg_params, + source->address, + (source->size - 8 - 256), + write_algorithm->address, + 0, + &armv7m_info); if (retval == ERROR_FLASH_OPERATION_FAILED) LOG_ERROR("error %d executing max32xxx flash write algorithm", retval); @@ -429,10 +487,9 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer, { struct max32xxx_flash_bank *info = bank->driver_priv; struct target *target = bank->target; - uint32_t flsh_cn, flsh_int; + uint32_t flash_cn, flash_int; uint32_t address = offset; uint32_t remaining = count; - uint32_t words_remaining; int retval; int retry; @@ -447,67 +504,74 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer, if (!info->probed) return ERROR_FLASH_BANK_NOT_PROBED; - if (offset & 0x3) { - LOG_WARNING("offset size must be word aligned"); - return ERROR_FLASH_DST_BREAKS_ALIGNMENT; + if ((info->options & OPTIONS_128) == 0) { + if (offset & 0x3) { + LOG_ERROR("offset size must be 32-bit aligned"); + return ERROR_FLASH_DST_BREAKS_ALIGNMENT; + } + } else { + if (offset & 0xF) { + LOG_ERROR("offset size must be 128-bit aligned"); + return ERROR_FLASH_DST_BREAKS_ALIGNMENT; + } } if (offset + count > bank->size) return ERROR_FLASH_DST_OUT_OF_BANK; - /* Prepare to issue flash operation */ + // Prepare to issue flash operation retval = max32xxx_flash_op_pre(bank); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + max32xxx_flash_op_post(bank); return retval; + } - if (remaining >= 4) { - /* write in 32-bit units */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - flsh_cn &= 0xF7FFFFFF; - flsh_cn |= 0x00000010; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); - - /* try using a block write */ - words_remaining = remaining / 4; - retval = max32xxx_write_block(bank, buffer, offset, words_remaining); + if (remaining >= 16) { + // try using a block write + retval = max32xxx_write_block(bank, buffer, offset, remaining); if (retval != ERROR_OK) { - if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) + if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) { + if (info->options & OPTIONS_ENC) { + LOG_ERROR("Must use algorithm in working area for encryption"); + return ERROR_FLASH_OPERATION_FAILED; + } LOG_DEBUG("writing flash word-at-a-time"); - else { + } else { max32xxx_flash_op_post(bank); return ERROR_FLASH_OPERATION_FAILED; } } else { - /* all 32-bit words have been written */ - buffer += words_remaining * 4; - address += words_remaining * 4; - remaining -= words_remaining * 4; + // all words_remaining have been written + buffer += remaining; + address += remaining; + remaining -= remaining; } } - if ((remaining >= 4) && ((address & 0x1F) != 0)) { - /* write in 32-bit units until we are 128-bit aligned */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - flsh_cn &= 0xF7FFFFFF; - flsh_cn |= 0x00000010; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + if (((info->options & OPTIONS_128) == 0) && remaining >= 4) { + // write in 32-bit units + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + flash_cn |= FLC_CN_32BIT; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); - while ((remaining >= 4) && ((address & 0x1F) != 0)) { - target_write_u32(target, info->flc_base + FLSH_ADDR, address); - target_write_buffer(target, info->flc_base + FLSH_DATA0, 4, buffer); - flsh_cn |= 0x00000001; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); - /* Wait until flash operation is complete */ + while (remaining >= 4) { + target_write_u32(target, info->flc_base + FLC_ADDR, address); + target_write_buffer(target, info->flc_base + FLC_DATA0, 4, buffer); + flash_cn |= FLC_CN_WR; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); + // Wait until flash operation is complete retry = 10; do { - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - } while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND)); + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + } while ((--retry > 0) && max32xxx_flash_busy(flash_cn)); if (retry <= 0) { - LOG_ERROR("Timed out waiting for flash write @ 0x%08" PRIx32, address); + LOG_ERROR("Timed out waiting for flash write @ 0x%08" PRIx32, + address); + max32xxx_flash_op_post(bank); return ERROR_FLASH_OPERATION_FAILED; } @@ -517,31 +581,32 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer, } } - if ((info->burst_size_bits == 128) && (remaining >= 16)) { - /* write in 128-bit bursts while we can */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - - flsh_cn &= 0xFFFFFFEF; - flsh_cn |= 0x08000000; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); - target_write_u32(target, info->flc_base + FLSH_ADDR, address); + if ((info->options & OPTIONS_128) && remaining >= 16) { + // write in 128-bit units + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + flash_cn &= ~(FLC_CN_32BIT); + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); while (remaining >= 16) { + target_write_u32(target, info->flc_base + FLC_ADDR, address); + if ((address & 0xFFF) == 0) LOG_DEBUG("Writing @ 0x%08" PRIx32, address); - target_write_buffer(target, info->flc_base + FLSH_DATA0, 16, buffer); - flsh_cn |= 0x00000001; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); - /* Wait until flash operation is complete */ + target_write_buffer(target, info->flc_base + FLC_DATA0, 16, buffer); + flash_cn |= FLC_CN_WR; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); + // Wait until flash operation is complete retry = 10; do { - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - } while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND)); + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + } while ((--retry > 0) && max32xxx_flash_busy(flash_cn)); if (retry <= 0) { - LOG_ERROR("Timed out waiting for flash write @ 0x%08" PRIx32, address); + LOG_ERROR("Timed out waiting for flash write @ 0x%08" PRIx32, + address); + max32xxx_flash_op_post(bank); return ERROR_FLASH_OPERATION_FAILED; } @@ -551,46 +616,14 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer, } } - if (remaining >= 4) { + if (((info->options & OPTIONS_128) == 0) && remaining > 0) { + // write remaining bytes in a 32-bit unit + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + flash_cn |= FLC_CN_32BIT; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); - /* write in 32-bit units while we can */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - flsh_cn &= 0xF7FFFFFF; - flsh_cn |= 0x00000010; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); - - while (remaining >= 4) { - target_write_u32(target, info->flc_base + FLSH_ADDR, address); - target_write_buffer(target, info->flc_base + FLSH_DATA0, 4, buffer); - flsh_cn |= 0x00000001; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); - /* Wait until flash operation is complete */ - retry = 10; - - do { - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - } while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND)); - - if (retry <= 0) { - LOG_ERROR("Timed out waiting for flash write @ 0x%08" PRIx32, address); - return ERROR_FLASH_OPERATION_FAILED; - } - - buffer += 4; - address += 4; - remaining -= 4; - } - } - - if (remaining > 0) { - /* write remaining bytes in a 32-bit unit */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - flsh_cn &= 0xF7FFFFFF; - flsh_cn |= 0x00000010; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); - - uint8_t last_word[4] = {0xff, 0xff, 0xff, 0xff}; - int i = 0; + uint8_t last_word[4] = {0xFF, 0xFF, 0xFF, 0xFF}; + uint32_t i = 0; while (remaining > 0) { last_word[i++] = *buffer; @@ -598,26 +631,77 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer, remaining--; } - target_write_u32(target, info->flc_base + FLSH_ADDR, address); - target_write_buffer(target, info->flc_base + FLSH_DATA0, 4, last_word); - flsh_cn |= 0x00000001; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); - /* Wait until flash operation is complete */ + target_write_u32(target, info->flc_base + FLC_ADDR, address); + target_write_buffer(target, info->flc_base + FLC_DATA0, 4, last_word); + flash_cn |= FLC_CN_WR; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); + + // Wait until flash operation is complete retry = 10; do { - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - } while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND)); + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + } while ((--retry > 0) && max32xxx_flash_busy(flash_cn)); if (retry <= 0) { LOG_ERROR("Timed out waiting for flash write @ 0x%08" PRIx32, address); + max32xxx_flash_op_post(bank); return ERROR_FLASH_OPERATION_FAILED; } } - /* Check access violations */ - target_read_u32(target, info->flc_base + FLSH_INT, &flsh_int); - if (flsh_int & FLSH_INT_AF) { + if ((info->options & OPTIONS_128) && remaining > 0) { + // write remaining bytes in a 128-bit unit + if (target_read_u32(target, info->flc_base + FLC_CN, &flash_cn) != ERROR_OK) { + max32xxx_flash_op_post(bank); + return ERROR_FAIL; + } + + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + flash_cn &= ~(FLC_CN_32BIT); + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); + + uint8_t last_words[16] = {0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}; + + uint32_t i = 0; + + while (remaining > 0) { + last_words[i++] = *buffer; + buffer++; + remaining--; + } + + target_write_u32(target, info->flc_base + FLC_ADDR, address); + target_write_buffer(target, info->flc_base + FLC_DATA0, 4, last_words); + target_write_buffer(target, info->flc_base + FLC_DATA0 + 4, 4, last_words + 4); + target_write_buffer(target, info->flc_base + FLC_DATA0 + 8, 4, last_words + 8); + target_write_buffer(target, info->flc_base + FLC_DATA0 + 12, 4, last_words + 12); + flash_cn |= FLC_CN_WR; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); + + // Wait until flash operation is complete + retry = 10; + do { + if (target_read_u32(target, info->flc_base + FLC_CN, + &flash_cn) != ERROR_OK) { + max32xxx_flash_op_post(bank); + return ERROR_FAIL; + } + } while ((--retry > 0) && (flash_cn & FLC_CN_PEND)); + + if (retry <= 0) { + LOG_ERROR("Timed out waiting for flash write @ 0x%08" PRIx32, address); + max32xxx_flash_op_post(bank); + return ERROR_FLASH_OPERATION_FAILED; + } + } + + // Check access violations + target_read_u32(target, info->flc_base + FLC_INT, &flash_int); + if (flash_int & FLC_INT_AF) { LOG_ERROR("Flash Error writing 0x%" PRIx32 " bytes at 0x%08" PRIx32, count, offset); max32xxx_flash_op_post(bank); return ERROR_FLASH_OPERATION_FAILED; @@ -638,7 +722,7 @@ static int max32xxx_probe(struct flash_bank *bank) free(bank->sectors); - /* provide this for the benefit of the NOR flash framework */ + // provide this for the benefit of the NOR flash framework bank->size = info->flash_size; bank->num_sectors = info->flash_size / info->sector_size; bank->sectors = calloc(bank->num_sectors, sizeof(struct flash_sector)); @@ -650,24 +734,24 @@ static int max32xxx_probe(struct flash_bank *bank) bank->sectors[i].is_protected = -1; } - /* Probe to determine if this part is in the max326xx family */ - info->max326xx = 0; + // Probe to determine if this part is in the max326xx family + info->max326xx = false; target_read_u32(target, ARM_PID_REG, &arm_id[0]); - target_read_u32(target, ARM_PID_REG+4, &arm_id[1]); + target_read_u32(target, ARM_PID_REG + 4, &arm_id[1]); arm_pid = (arm_id[1] << 8) + arm_id[0]; LOG_DEBUG("arm_pid = 0x%x", arm_pid); - if ((arm_pid == ARM_PID_DEFAULT_CM3) || arm_pid == ARM_PID_DEFAULT_CM4) { + if (arm_pid == ARM_PID_DEFAULT_CM3 || arm_pid == ARM_PID_DEFAULT_CM4) { uint32_t max326xx_id; target_read_u32(target, MAX326XX_ID_REG, &max326xx_id); LOG_DEBUG("max326xx_id = 0x%" PRIx32, max326xx_id); max326xx_id = ((max326xx_id & 0xFF000000) >> 24); if (max326xx_id == MAX326XX_ID) - info->max326xx = 1; + info->max326xx = true; } LOG_DEBUG("info->max326xx = %d", info->max326xx); - /* Initialize the protection bits for each flash page */ + // Initialize the protection bits for each flash page if (max32xxx_protect_check(bank) == ERROR_FLASH_OPER_UNSUPPORTED) LOG_WARNING("Flash protection not supported on this device"); @@ -679,7 +763,7 @@ static int max32xxx_mass_erase(struct flash_bank *bank) { struct target *target = NULL; struct max32xxx_flash_bank *info = NULL; - uint32_t flsh_cn, flsh_int; + uint32_t flash_cn, flash_int; int retval; int retry; info = bank->driver_priv; @@ -693,50 +777,50 @@ static int max32xxx_mass_erase(struct flash_bank *bank) if (!info->probed) return ERROR_FLASH_BANK_NOT_PROBED; - int not_protected = 0; + bool protected = true; for (unsigned int i = 0; i < bank->num_sectors; i++) { if (bank->sectors[i].is_protected == 1) LOG_WARNING("Flash sector %u is protected", i); else - not_protected = 1; + protected = false; } - if (!not_protected) { + if (protected) { LOG_ERROR("All pages protected"); return ERROR_FAIL; } - /* Prepare to issue flash operation */ + // Prepare to issue flash operation retval = max32xxx_flash_op_pre(bank); if (retval != ERROR_OK) return retval; - /* Write mass erase code */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - flsh_cn |= FLSH_CN_ERASE_CODE_ME; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + // Write mass erase code + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + flash_cn |= FLC_CN_ERASE_CODE_ME; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); - /* Issue mass erase command */ - flsh_cn |= 0x2; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + // Issue mass erase command + flash_cn |= FLC_CN_ME; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); - /* Wait until erase complete */ + // Wait until erase complete retry = 1000; do { - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - } while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND)); + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + } while ((--retry > 0) && max32xxx_flash_busy(flash_cn)); if (retry <= 0) { LOG_ERROR("Timed out waiting for flash mass erase"); return ERROR_FLASH_OPERATION_FAILED; } - /* Check access violations */ - target_read_u32(target, info->flc_base + FLSH_INT, &flsh_int); - if (flsh_int & FLSH_INT_AF) { + // Check access violations + target_read_u32(target, info->flc_base + FLC_INT, &flash_int); + if (flash_int & FLC_INT_AF) { LOG_ERROR("Error mass erasing"); - target_write_u32(target, info->flc_base + FLSH_INT, 0); + target_write_u32(target, info->flc_base + FLC_INT, 0); return ERROR_FLASH_OPERATION_FAILED; } @@ -784,34 +868,34 @@ COMMAND_HANDLER(max32xxx_handle_protection_set_command) return retval; info = bank->driver_priv; - /* Convert the range to the page numbers */ - if (sscanf(CMD_ARGV[1], "0x%"SCNx32, &addr) != 1) { + // Convert the range to the page numbers + if (sscanf(CMD_ARGV[1], "0x%" SCNx32, &addr) != 1) { LOG_WARNING("Error parsing address"); command_print(CMD, "max32xxx protection_set "); return ERROR_FAIL; } - /* Mask off the top portion on the address */ + // Mask off the top portion on the address addr = (addr & 0x0FFFFFFF); - if (sscanf(CMD_ARGV[2], "0x%"SCNx32, &len) != 1) { + if (sscanf(CMD_ARGV[2], "0x%" SCNx32, &len) != 1) { LOG_WARNING("Error parsing length"); command_print(CMD, "max32xxx protection_set "); return ERROR_FAIL; } - /* Check the address is in the range of the flash */ - if ((addr+len) >= info->flash_size) + // Check the address is in the range of the flash + if ((addr + len) >= info->flash_size) return ERROR_FLASH_SECTOR_INVALID; if (len == 0) return ERROR_OK; - /* Convert the address and length to the page boundaries */ + // Convert the address and length to the page boundaries addr = addr - (addr % info->sector_size); if (len % info->sector_size) len = len + info->sector_size - (len % info->sector_size); - /* Convert the address and length to page numbers */ + // Convert the address and length to page numbers addr = (addr / info->sector_size); len = addr + (len / info->sector_size) - 1; @@ -840,34 +924,34 @@ COMMAND_HANDLER(max32xxx_handle_protection_clr_command) return retval; info = bank->driver_priv; - /* Convert the range to the page numbers */ - if (sscanf(CMD_ARGV[1], "0x%"SCNx32, &addr) != 1) { + // Convert the range to the page numbers + if (sscanf(CMD_ARGV[1], "0x%" SCNx32, &addr) != 1) { LOG_WARNING("Error parsing address"); command_print(CMD, "max32xxx protection_clr "); return ERROR_FAIL; } - /* Mask off the top portion on the address */ + // Mask off the top portion on the address addr = (addr & 0x0FFFFFFF); - if (sscanf(CMD_ARGV[2], "0x%"SCNx32, &len) != 1) { + if (sscanf(CMD_ARGV[2], "0x%" SCNx32, &len) != 1) { LOG_WARNING("Error parsing length"); command_print(CMD, "max32xxx protection_clr "); return ERROR_FAIL; } - /* Check the address is in the range of the flash */ - if ((addr+len) >= info->flash_size) + // Check the address is in the range of the flash + if ((addr + len) >= info->flash_size) return ERROR_FLASH_SECTOR_INVALID; if (len == 0) return ERROR_OK; - /* Convert the address and length to the page boundaries */ + // Convert the address and length to the page boundaries addr = addr - (addr % info->sector_size); if (len % info->sector_size) len = len + info->sector_size - (len % info->sector_size); - /* Convert the address and length to page numbers */ + // Convert the address and length to page numbers addr = (addr / info->sector_size); len = addr + (len / info->sector_size) - 1; @@ -895,7 +979,7 @@ COMMAND_HANDLER(max32xxx_handle_protection_check_command) return retval; info = bank->driver_priv; - /* Update the protection array */ + // Update the protection array retval = max32xxx_protect_check(bank); if (retval != ERROR_OK) { LOG_WARNING("Error updating the protection array"); @@ -905,10 +989,10 @@ COMMAND_HANDLER(max32xxx_handle_protection_check_command) LOG_WARNING("s: a:
p:"); for (unsigned int i = 0; i < bank->num_sectors; i += 4) { LOG_WARNING("s:%03d a:0x%06x p:%d | s:%03d a:0x%06x p:%d | s:%03d a:0x%06x p:%d | s:%03d a:0x%06x p:%d", - (i+0), (i+0)*info->sector_size, bank->sectors[(i+0)].is_protected, - (i+1), (i+1)*info->sector_size, bank->sectors[(i+1)].is_protected, - (i+2), (i+2)*info->sector_size, bank->sectors[(i+2)].is_protected, - (i+3), (i+3)*info->sector_size, bank->sectors[(i+3)].is_protected); + (i + 0), (i + 0) * info->sector_size, bank->sectors[(i + 0)].is_protected, + (i + 1), (i + 1) * info->sector_size, bank->sectors[(i + 1)].is_protected, + (i + 2), (i + 2) * info->sector_size, bank->sectors[(i + 2)].is_protected, + (i + 3), (i + 3) * info->sector_size, bank->sectors[(i + 3)].is_protected); } return ERROR_OK; @@ -970,4 +1054,5 @@ const struct flash_driver max32xxx_flash = { .erase_check = default_flash_blank_check, .protect_check = max32xxx_protect_check, .info = get_info, + .free_driver_priv = default_flash_free_driver_priv, };