Do not echo the selected reset config. This is one of many changes to
make the behavior of Tcl commands more consistent.
This also avoids stray and confusing messages in the output of OpenOCD.
For example, the "reset_config" line here:
Open On-Chip Debugger 0.12.0+dev-00802-gb7f0145fc-dirty
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
cortex_m reset_config sysresetreq
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
While at it, fix some coding style and command handling issues.
Change-Id: I3b3d8687af1d23a2dc1764f29b52dc607b80cb59
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8638
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The coding style requires the 'case' to be at the same indentation
level of its 'switch' statement.
Align the code accordingly.
While there:
- add space around the operators;
- drop useless empty line.
Skip all riscv code, as it is going to be updated soon from the
external fork.
No changes are reported by
git log -p -w --ignore-blank-lines --patience
Change-Id: I2691dfdd2b6734143e14160b46183623e9773539
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9051
Tested-by: jenkins
Format strings are often split to allow using the conversion
specifiers macros from <inttypes.h>.
When the format string ends with one of such macros, there is no
need to add an empty string "" after the macro.
In current code we have 203 cases of empty string present, against
1159 cases of string ending with the macro.
Uniform the style across OpenOCD by removing the empty string.
Don't modify the files 'angie.c' and 'max32xxx.c' as they are
already changed by other independent commits.
Change-Id: I23f1120101ce1da67c6578635fc6507a58c803e9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9065
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Running target algorithms on ARMv8M may require core in secure
mode with SAU and MPU off (as set after reset).
cortex_m_set_secure() forces this mode with optional save of
the previous state.
cortex_m_security_restore() restores previously saved state.
Change-Id: Ia71826db47ee7b0557eaffd55244ce13eacbcb4b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8959
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
[1] removed target_halt() from cortex_m_assert_reset()
It broke debug_reason tracking and the previous reason
was shown after reset halt.
Set debug_reason to DBG_REASON_DBGRQ during reset halt
preparation.
Fixes: [1] commit 226085065b ("target/cortex_m: drop useless target_halt() call")
Reported-by: Marc Schink <dev@zapb.de>
Change-Id: I685618ed158abde11f6e00eeeee1dfa8ed90952d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8945
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
The parameter Jim_Interp to the target API target_create() is not
used by any target.
Drop it.
Change-Id: I67c492078a6c808db974505f9e297c45165f64d0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8831
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Deasserting is useless if reset was not asserted except the very corner
case: changed reset_config during reset processing.
Change-Id: I1d1ea142980d67293daa348a2869b68ffd78d0eb
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8734
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
In multi-target SoC not all the targets are running simultaneously
and some target could be powered off or kept under reset.
Commit 4892e32294 ("target/cortex_m: allow poll quickly get out
of TARGET_RESET state") does not considers the case of a target
that is kept in reset and expects the target to change state from
TARGET_RESET immediately.
This causes OpenOCD to log continuously:
Info : [stm32mp15x.cm4] external reset detected
Info : [stm32mp15x.cm4] external reset detected
Info : [stm32mp15x.cm4] external reset detected
Read again dhcsr to detect the 'stable' reset status and quit,
waiting for next poll to re-check the target's status.
Change-Id: Ic66029b988404a1599bb99bc66d4a8845b8b02c6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 4892e32294 ("target/cortex_m: allow poll quickly get out of TARGET_RESET state")
Reviewed-on: https://review.openocd.org/c/openocd/+/8399
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Fix checkpatch errors:
ERROR:BOOL_COMPARISON: Using comparison to true/false is
error prone
While there,
- drop useless parenthesis,
- drop unnecessary else after a return.
Change-Id: I1234737b3e65bd10df5e938d1c36f9abaf02d348
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8496
Reviewed-by: zapb <dev@zapb.de>
Tested-by: jenkins
Conversion done with
checkpatch --fix-inplace -types UNSPECIFIED_INT
Ignore the cast as they could be better addressed.
Fix only minor additional checkpatch issue (spacing and line
length).
Use Checkpatch-ignore below for the function pointers in the file
'armv7a_cache_l2x.h' that do not assign the identifier names to
the function arguments.
Most of these struct are unused and should be fixed or dropped.
Checkpatch-ignore: FUNCTION_ARGUMENTS
Change-Id: I8f27e68eb3502e431c1ba801b362358105f9f2dc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8480
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Detected while converting 'unsigned' to 'unsigned int'.
Use the correct conversion string for stdint values.
Change-Id: I99f3dff4c64dfd7acf2bddb130b56e9ebe1e6c60
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8477
Tested-by: jenkins
Scan-build is unable to detect that 'target->dbg_msg_enabled' does
not change across the function cortex_m_fast_read_all_regs().
It incorrectly assumes that it can be false at the first check (so
'dcrdr' get not assigned) and it is true later on (when 'dcrdr'
get used).
This triggers a false positive:
src/target/cortex_m.c:338:12: warning:
3rd function call argument is an uninitialized value
[core.CallAndMessage]
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
Use a local variable for 'target->dbg_msg_enabled' so scan-build
can track it as not modified.
While there, change the type of 'target->dbg_msg_enabled' to
boolean as there is no reason to use uint32_t.
Change-Id: Icaf1a1b2dea8bc55108182ea440708ab76396cd7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8391
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
ARM documentation for Cortex-M reports the field 'implementer' in
the register CPUID.
OpenOCD used the miss-spelled 'implementor'. Fix it!
Change-Id: I854d223971ae7a49346e1f7491c2c0415f5e2c1d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8318
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Add Cortex-M52 to the list of known Cortex-M implementations to
allow detection of the core.
Values checked against the ARM document "Arm China Cortex®-M52
Processor Technical Reference Manual" 102776_0002_06_en.
Reported-by: Joseph Yiu <Joseph.Yiu@arm.com>
Change-Id: Id0bde8a0476f76799b7274835db9690f975e2dd6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8317
Tested-by: jenkins
When an asynchronous exception occurs at the same time
as a breakpoint event (either hardware breakpoint or software breakpoint),
it is possible for the processor to halt at the beginning of the
exception handler instead of the instruction address pointed
by the breakpoint.
During debug entry in exception handler state and with BKPT bit set
as the only break reason in DFSR, check if there is a breakpoint, which
have triggered the debug halt. If there is no such breakpoint,
resume execution. The processor services the interrupt and
halts again at the correct breakpoint address.
The workaround is not needed during target algo run (debug_execution)
because interrupts are disabled in PRIMASK register.
Also after single step the workaround resume never takes place:
the situation is treated as error.
Link: https://developer.arm.com/documentation/SDEN1068427/latest/
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I8b23f39cedd7dccabe7e7066d616fb972b69f769
Reviewed-on: https://review.openocd.org/c/openocd/+/8332
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Liviu Ionescu
Commit f9509c92db ("itm: rework itm commands before 'init'")
ignores the default enable of ITM channel 0, that is applied when
no 'itm port[s]' is issued.
Call armv7m_trace_itm_config() unconditionally to handle it.
Change-Id: I3e85d0b063ed38c1552f6af9ea9eea2e76aa9025
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Paul Fertser <fercerpav@gmail.com>
Fixes: f9509c92db ("itm: rework itm commands before 'init'")
Reviewed-on: https://review.openocd.org/c/openocd/+/7900
Reviewed-by: <post@frankplowman.com>
Tested-by: jenkins
cortex_m_poll_one() detects reset testing S_RESET_ST sticky bit.
If the signal comes unexpectedly, poll must return TARGET_RESET state.
On the contrary in case of polling inside of an OpenOCD reset command,
TARGET_RESET has been has already been set and we need to get out of
it as quickly as possible.
The original code needs 2 polls: the first clears S_RESET_ST
and keeps TARGET_RESET state, the current TARGET_RUNNING or TARGET_HALTED
is reflected as late as the second poll is done.
Change the logic to keep in TARGET_RESET only when necessary.
See also [1]
Link: [1] 8284: tcl/target: ti_cc3220sf: Use halt for CC3320SF targets | https://review.openocd.org/c/openocd/+/8284
Fixes: https://sourceforge.net/p/openocd/tickets/360/
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I759461e5f89ca48a6e16e4b4101570260421dba1
Reviewed-on: https://review.openocd.org/c/openocd/+/8285
Tested-by: jenkins
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Prevent a segmentation fault by preventing to try to halt a target
that has not been examined yet.
Change-Id: I5d344e7fbdb5422f7c5e2c39bdd48cbc6c2a3e58
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8213
Tested-by: jenkins
Commit 16b4b8cf54 ("Cortex-M3: expose most DWT registers") added
the DWT registers to the list of CPU registers.
The commit message from 2009 reports the reason behind this odd
mixing of CPU and DWT registers.
This feature got broken in 2017 with the introduction of the field
struct reg::exist and its further use in the code. As result, the
command 'reg' on a target Cortex-M reports only the core registers
and then the header line
===== Cortex-M DWT registers
not anymore followed by the DWT registers.
Fix it by tagging each DWT registers as existing.
Change-Id: Iab026e7da8d6b8ba052514c3fd3b5cdfe301f330
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: b5964191f0 ("register: support non-existent registers")
Reviewed-on: https://review.openocd.org/c/openocd/+/8198
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Fix obsoleted references to Cortex-M3 from the time
when M3 was the only supported Cortex.
Fix typo.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I6f93265f1b9328fec063fecd819210deb28aaf2c
Reviewed-on: https://review.openocd.org/c/openocd/+/8099
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In 2008 the commit 1829361253 ("define resetting
the target into the halted or running state as an atomic operation.")
introduced the target_halt() call to the end of cortex_m3_assert_reset(),
Checkpatch-ignore: GIT_COMMIT_ID
A year later the commit ed36a8d15d
("... Updated halt handling for cortex_m3")
prevented cortex_m3_halt() take any action in case of TARGET_RESET state.
This narrowed the target_halt() called from cortex_m3_assert_reset()
to setting target->halt_issued and storing a time stamp.
Introducing ocd_process_reset(_inner) made the setting of halt_issued
and halt_issued_time useless. The Tcl function waits for halt
of all targets if applicable.
cortex_m_halt() and also target_halt() does not work as expected
if the cached target state is TARGET_RESET (although the core could
be out of reset and ready to be halted, just have not been polled).
Explicit Tcl arp_poll must be issued in many scenarios.
Remove the useless hack.
Also remove the explicit error return from cortex_m_halt_one()
in case of RESET_SRST_PULLS_TRST and asserted srst. If the communication
with the target is gated by any reset, cortex_m_write_debug_halt_mask()
fails. Propagate the error return of this call instead.
Change-Id: I0da05b87f43c3d0facb78e54d8f00c1728fe7c46
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8098
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In a corner case when debug_ap is not available,
cortex_m_assert_reset() asserts reset to restore
communication with the target.
Prevent to do so on targets with defer_examine,
as such targets need some special handling to enable them
after reset anyway.
The change makes possible to handle a multicore Cortex-M SoC with
an auxiliary Cortex-M core(s) switched of by default
even with 'reset_config srst_gates_jtag'
Change-Id: I8cec7a816423e588d5e2e4f7904c81c776eddc42
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8097
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For Armv8.1-M based cores, detect if the core implements the optional
M-profile vector extension (MVE), using MVFR1 register.
While at there rework armv7m->fp_feature detection based on MVFR0
and MVFR1 registers.
Change-Id: I92d5b1759aea9f7561d285f46acdec51d6efb7b4
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6950
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
These cores are advertised as M23 and M33 compatible, but are identified
by the Realtek implementor id. These cores are found on the RTL872xD
family, at least.
Raw CPUIDs:
Real-M200 (KM0): 721cd200
Real-M300 (KM4): 721fd220
Change-Id: I4106ccb7e8c562f98072a71e9e818f57999d664e
Signed-off-by: Karl Palsson <karlp@tweak.au>
Reviewed-on: https://review.openocd.org/c/openocd/+/7846
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Presently, we only look at the Part Number field of the CPUID, and
completely ignore the Implmentor field, simply assuming it to be ARM.
Parts have since been found, with different implementors, that use
overlapping part numbers, causing detection to fail.
Expand the "part number" field to be a full implementor+part number,
excluding the revision/patch fields, to make checking more reliable.
Change-Id: Id81774f829104f57a0c105320d0d2e479fa01522
Signed-off-by: Karl Palsson <karlp@tweak.au>
Reviewed-on: https://review.openocd.org/c/openocd/+/7845
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This patch changes data types of watchpoint value and mask to allow for
64-bit values match that some architectures (like RISCV) allow.
In addition this patch fixes the behavior of watchpoint command to
zero-out mask if only data value is provided.
Change-Id: I3c7ec1630f03ea9534ec34c0ebe99e08ea56e7f0
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7840
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Lot of messages was logged as LOG_WARNING, but the operation failed
immediately. Sometimes no error message was logged at all.
Add missing messages, change warnings to errors.
Sometimes ERROR_TARGET_INVALID was returned. Some command handlers
returned ERROR_OK! Always return ERROR_TARGET_NOT_HALTED.
While on it use LOG_TARGET_ERROR() whenever possible.
Prefix command_print() message with 'Error:' to get closer
to LOG_TARGET_ERROR() variant.
Error message was not added to get() and set() methods of
struct xxx_reg_type - the return value is properly checked and a message
is logged by the caller in case of ERROR_TARGET_NOT_HALTED.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I2fe4187c6025f0038956ab387edbf3f461c69398
Reviewed-on: https://review.openocd.org/c/openocd/+/7819
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Value in the 'dscsr' variable is garbage until the DAP queue is run.
Postpone evaluation of the 'secure_state' variable. Reading the
core registers in between will execute the DAP queue.
Change-Id: I44959e882dbafb1b9779e813c3d13f3b3dbcd47f
Signed-off-by: Bohdan Tymkiv <bohdan200@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7693
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
For some trivial case only, replace calls to jim-nvp with calls
to the new OpenOCD nvp.
Change-Id: Ifd9aff32b67748af8ab808e6a6b6e64f5271b888
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7553
Tested-by: jenkins
Cortex-M support for SMP multicore targets.
This SMP implementation unlike older ones does not act
on the first halted target found. It polls targets
until a SMP group is finished and stores eventual
'halted' events instead of emitting them. As soon as polling
of a group is done, poll proceeds with SMP related tasks.
This approach improves detection of a reason why debug
stopped - a correct reason is detected for all targets,
not only for the first found.
Drawback: SMP target group should be defined in the same
order as the targets were defined.
Obsolete gdb 'J' packet/smp_gdb command core switching is not implemented,
use with rtos hwthread.
Only one core is resumed if debug_execution is requested.
Some ideas taken from Graham Sanderson's [4936]
and src/target/aarch64.c
Added error checking of armv7m_restore_context().
Change-Id: I60f5b79e74b624dc2b5835ff10e38ac2ccb23792
Link: [4936]: target/cortex_m: Add smp support for Cortex M | https://review.openocd.org/c/openocd/+/4936
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7239
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Cores armv8m, e.g. Cortex-M33, can be instantiated without the
optional Security Extension.
In this case, the secure registers are not present and when GDB
try accessing them it triggers a set of errors.
For armv8m cores without security extension, don't provide to GDB
the description of the secure registers.
Change-Id: I254478a4cf883e85b786df3f62c726b2f40d88d9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7402
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Commit 35a503b08d ("arm_adi_v5: add ap refcount and add get/put
around ap use") modifies the examine functions of mem_ap, cortex_m,
cortex_a and aarch64 by calling dap_put_ap() and then looking again
for the mem-ap and calling dap_get_ap().
This causes an issue if the system is irresponsive and the examine
fails and left the AP pointer to NULL. If the system was already
examined the NULL pointer will cause a SIGSEGV.
Commit b6dad912b8 ("target/cortex_m: prevent segmentation fault
in cortex_m_poll()") proposes a fix for one specific case and only
on cortex_m.
Modify all the examine functions by skipping look-up for the AP if
it was already set in a previous examine; the target's AP is not
supposed to change during runtime.
Remove the partial fix for cortex_m as it is not needed anymore.
Change-Id: I806ec3b1b02fcc76e141c8dd3a65044febbf0a8c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 35a503b08d ("arm_adi_v5: add ap refcount and add get/put around ap use")
Reviewed-on: https://review.openocd.org/c/openocd/+/7392
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
An application often idling in real sleep mode may make a Cortex-M target
hard to access as CPU clock are gated and debug requests are responded
by WAIT ack.
Try to examine the target under reset as the last resort.
Change-Id: Ife875a966a838c37dde987bc584ad0a1f4d020d6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7228
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
After merging [1] 'reset halt' does not work on not responding Cortex-M.
Relax the examined tests and try to set vector catch VC_CORERESET
if debug_ap is available.
While on it add an info about examination state to debug logs.
Fixes: [1] commit 98d9f1168c ("target: reset target examined flag if target::examine() fails")
Change-Id: Ie2e018610026180af5997d70231061a275f05c76
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6745
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
With the old checkpatch we cannot use the correct format for the
SPDX tags in the file .c, in fact the C99 comments are not allowed
and we had to use the block comment.
With the new checkpatch, let's switch to the correct SPDX format.
Change created automatically through the command:
sed -i \
's,^/\* *\(SPDX-License-Identifier: .*[^ ]\) *\*/$,// \1,' \
$(find src/ contrib/ -name \*.c)
Change-Id: I6da16506baa7af718947562505dd49606d124171
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7153
Tested-by: jenkins
We have left the camelcase symbols *xPSR* for some time, to avoid
any conflict with possibly pending patches in gerrit.
With the approaching v0.12.0-rc1, it's time to revisit it.
The patches in gerrit that conflict with this rename are all not
merge-able due to conflicts or due to negative review.
Drop these CamelCase symbols.
Change-Id: Ifbac4c1df9cc55994e024971a2aaebeed2ea4ed3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7155
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The S_RESET_ST sticky bit is reset after DHCSR read.
It is set at power-on reset and keeps active until the debuger reads DHCSR.
Ignore S_RESET_ST at the very first read after OpenOCD start
and suppress possibly misleading message "external reset detected"
if we cannot guarantee the reset happened recently.
While on it add a TODO comment.
Change-Id: I15217c2ca6f69ac97aff8be86bce67cba94a42cd
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7109
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
If a Cortex-M MCU become unresponsive during a debug session and
re-examination fails to find MEM-AP, debug_ap pointer is set to NULL.
Eventual call of cortex_m_poll() dereferences debug_ap.
Check debug_ap validity at the begin of cortex_m_poll().
Change-Id: I9519f48760c91a48a9e5e8c34634d247098cb14a
Fixes: 35a503b08d (arm_adi_v5: add ap refcount and add get/put around ap use)
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7108
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Replace the FSF boilerplate with the SPDX tag.
The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.
Change-Id: I255ad17235ff1e01bf0aa4deed4d944e1d693ddb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7071
Tested-by: jenkins
While an ADIv5 DAP can only have 256 AP, ADIv6 can provide till
2**40 (1,099,511,627,776) AP per DAP.
The actual trivial code implementation for ADIv5 (that uses an
array of 256 ap in the struct adiv5_dap) cannot be extended as-is
to handle ADIv6.
The simple array of 256 AP can be reused as a dynamic storage for
ADIv6 ap:
- the ADIv5 AP number is replaced by the ADIv6 base address;
- the index of the array (equal to ADIv5 AP number) has no link to
any ADIv6 property;
- the ADIv6 base_address has to be searched in the array of AP.
The 256 elements in the AP array should be enough for any device
available today. In future it can be easily increased, if needed.
To efficiently use the 256 elements in the AP array, the code
should associate one element of the array to an ADIv6 AP (through
the AP base address), then cancel the association when the AP is
not anymore needed. This is important to avoid saturating the AP
array while exploring the device through 'dap apreg' commands.
Add a reference counter in the struct adiv5_ap to track how many
times the struct has been associated with the same base address.
Introduce the function dap_get_ap() to associate and return the
struct, and dap_put_ap() to release the struct. For the moment the
code covers ADIv5 only, so the association is through the index.
Use the two functions above and dap_find_get_ap() throughout the
code.
Check the return value of dap_get_ap(). It is always not NULL in
the current ADIv5-only implementation, but can be NULL for ADIv6
when there are no more available AP in the array.
Instrument dap_queue_ap_read() and dap_queue_ap_write() to log an
error message if the AP has reference counter zero, meaning that
the AP has not been 'get' yet. This helps identifying AP used
without get/put, e.g. code missed by this patch, or merged later.
Instrument dap_cleanup_all() to log an error message if an AP has
reference counter not zero at openocd exit, meaning that the AP
has not been 'put' yet.
Change-Id: I98316eb42b9f3d9c9bbbb6c73b1091b53f629092
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6455
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Tested-by: jenkins
The 'set' variable name suggests a boolean data type which determines
whether a breakpoint (or watchpoint) is active. However, it is also
used to store the number of the breakpoint.
This encoding leads to inconsistent value assignments: boolean and
integer values are mixed. Also, associated hardware comparator
numbers, which are usually numbered from 0, cannot be used directly.
An additional offset is required to store the comparator numbers.
In order to make the code more readable and the value assignment more
consistent, change the variable name to 'is_set', its data type to 'bool'
and introduce a dedicated variable for the break-/watchpoint
number.
In order to make the review easier, the data types of various related
variables (e.g. number of breakpoints) are not changed.
While at it, fix a few coding style issues.
Change-Id: I2193f5639247cce6b80580d4c1c6afee916aeb82
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6319
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
