3cff4213a4
Merge pull request #69 from riscv/multi-gdb
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Fix the multi-GDB mode bugs
2017-07-03 13:18:06 -07:00
f18fd83ac7
Fix trigger set/clear bug.
2017-07-03 11:52:35 -07:00
99a3673507
Fix comment about saving the temporary register in examine procedure.
2017-07-01 15:09:23 +03:00
7d451e00f5
Restore value of temporary register (s0) in examine OpenOCD procedure in case of core can not execute 64 bit instruction.
2017-06-30 19:15:58 +03:00
d77c4a953c
Don't set breakpoints on disabled harts
2017-06-21 12:25:20 -07:00
689d0fcaf6
No longer hard-code the non-RTOS hart to 0
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I was just being lazy here.
2017-06-21 12:25:19 -07:00
4bdb042224
Allow memory writes to proceed on all harts
2017-06-21 12:25:19 -07:00
a277416a39
Refactor examine, to avoid some assertions
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Now that we're supporting non-RTOS multi-hart mode there's some more
assertions that you're running on the right hart. Those assertions
aren't sane very early in examine, so I avoid them.
2017-06-21 12:25:19 -07:00
788908fcf0
Factor out checking if harts should be used
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Rather than having a bunch of "if rtos" stuff, I now just check "if
hart_enabled". This makes some code paths cleaner, all of which were
buggy in the non-RTOS multi-hart mode.
2017-06-21 10:09:16 -07:00
9f4cac5a38
Set current_hartid from coreid
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This avoids a bunch of RTOS special cases.
2017-06-20 17:19:05 -07:00
9cd98058a0
Set hardware triggers on all harts.
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Right now we're using "threads" to represent harts. gdb/OpenOCD assume
there's only one set of hardware breakpoints among all threads. Make it
so.
2017-06-20 13:10:35 -07:00
10518351bb
Don't immediately segfault with -rtos on v0.11.
2017-06-20 11:32:42 -07:00
ccdd26e3ef
Comment curious code.
2017-06-20 11:32:42 -07:00
927f9d8873
Update list of "threads" when harts are discovered.
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This ensures that "info threads" is accurate as soon as gdb connects.
Also print out number of triggers that is discovered in examine().
2017-06-20 11:32:42 -07:00
4d264b3579
Put early DEBUG notice of XLEN back.
2017-06-19 08:46:02 -07:00
6082f35a55
Update debug_defines. Clarify debug output.
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Update debug_defines from the spec, commit 920ec9a690.
Decode dmstatus scans in the debug output.
2017-06-16 14:02:25 -07:00
fd81f7fcac
Fix comment.
2017-06-16 14:02:25 -07:00
851849a295
Tell the user about detected harts.
2017-06-16 14:02:25 -07:00
3abb347bd9
Tighten up debug output.
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Assuming the program allocating code works, we don't need its output.
Only output parts of the debug RAM that are actually doing something.
2017-06-16 14:02:25 -07:00
ac2da40f74
Fix indentation to match OpenOCD style.
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This change is just in the whitespace. There are no code changes.
See http://openocd.org/doc-release/doxygen/stylec.html
2017-06-15 12:44:50 -07:00
363a0a2bf2
Merge pull request #64 from riscv/release-fixes
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Two fixes from the release branch
2017-06-15 12:43:46 -07:00
50a223ef9a
Fix print statements to work with 64-bit addresses
2017-06-15 12:24:37 -07:00
afc9eb6c47
Jump to the RTOS hartid after halting
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When I disappeared the polls everywhere I forgot to sanitize the hartid
after halting. This is an invariant that GDB expects: when you return
from a halt whatever thread is marked as currently selected is the
thread that the next register accesses reference.
2017-06-15 12:16:33 -07:00
099a3020d2
Clear abstract errors from register_read_direct
2017-06-15 12:16:24 -07:00
64af052911
Fix the build.
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Main change is to make riscv_addr_t be unsigned. The rest is mechanical
fixing of types, print statements, and a few signed/unsigned compares.
Smoketest indicates everything is working more or less as before.
2017-06-13 12:33:01 -07:00
6be600318c
Fix dmi_read() indentation; remove \n in LOG_ERROR
2017-06-08 12:31:08 -07:00
c3b344d1c0
riscv: Move the initialization of the field inside the structure for consistency
2017-06-07 21:06:33 -07:00
459b39ec67
riscv: v13 -- dmi_write must still check for the OP result
2017-06-07 21:06:33 -07:00
11008baee3
%p already includes 0x (on gcc)
2017-06-06 11:51:15 -07:00
ab77c5d792
Invalidate the register cache when rtos_hartid==-1
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This means I don't know what hart to look at, so I might as well
invalidate the register cache. Without this, you might get stale
registers the first time you ask for them.
2017-05-25 13:14:31 -07:00
faa6123e36
Invalidate the register cache on step, resume, reset
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I thought OpenOCD did this, but it looks like that doesn't happen when
runningi in RTOS mode. With this I can get to the end of most of the
RTOS tests, but they SIGINT instead of exiting.
2017-05-25 13:14:31 -07:00
e12f5575ef
riscv-v11: Don't perform unexpected operation in cache_write
2017-05-22 22:02:01 -07:00
c431c0eb25
Check for abstractcs.busy, not just CMDERR_BUSY
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This fixes a race condition when reading/writing memory.
2017-05-15 17:40:28 -07:00
a8cf04b839
Go back to 32-word read/write buffers
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The larger buffers are really slow on Spike.
2017-05-15 16:57:25 -07:00
e31761df64
Don't re-read registers after they're written
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This was just a sanity check.
2017-05-15 16:57:08 -07:00
9d308db2bc
Print out the actual CSR that's read
2017-05-15 16:56:50 -07:00
8252b9d36c
Build fixes
2017-05-15 13:39:58 -07:00
af6e04d5c0
riscv: Remove some compile warnings
2017-05-15 13:36:05 -07:00
bcf2a16b0d
Shim back in some old interfaces for now
2017-05-11 10:41:13 -07:00
563f6acc3c
Allow all harts to be reset
2017-05-09 13:33:20 -07:00
fa8d7adf33
Avoid accessing null target->reg_cache
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GDB might request registers even if target was not successfully initialized.
2017-05-05 11:05:28 -07:00
95a2eb157a
riscv-013: more consistent parens
2017-05-01 09:42:11 -07:00
458bb20699
riscv-013: Correct sign extension of address on read_memory for lower bits as well
2017-05-01 09:39:59 -07:00
8462750357
riscv-013: Correct sign extension of address on read_memory
2017-05-01 09:37:48 -07:00
ad1cf13ef4
Correct debugging print in read_memory
2017-05-01 08:35:10 -07:00
16de5044d4
Fix an assertion when reading from 0
2017-05-01 08:33:01 -07:00
ba3a56937b
Correct previous hart caching logic
2017-05-01 08:32:43 -07:00
1ec607c726
Clean up unused read_memory code
2017-04-27 12:56:01 -07:00
17d04aded3
Keep calling the old poll on v0.11 targets
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This is another thing that should be fixed correctly. Essentially this
just uses the old codepath, which works for v0.11.
2017-04-26 15:16:39 -07:00
9d4df3420c
Initialize all registers in examine
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I'm not sure why this is necessary, but for some reason GDB is asking
for registers before OpenOCD thinks there's been a halt. This is really
just a workaround, but I need to refactor the v0.11 stuff anyway so I
don't want to figure it out.
2017-04-26 15:09:24 -07:00
Palmer Dabbelt