The mips opcode macro for the SRL opcode was using the wrong constant
value:
SRA -- Shift right arithmetic
Encoding: 0000 00-- ---t tttt dddd dhhh hh00 0011
SRL -- Shift right logical
Encoding: 0000 00-- ---t tttt dddd dhhh hh00 0010
This corrects the opcode constant for SRL and adds the SRA opcode for
completeness.
There is only one user of MIPS32_OP_SRL in src/flash/nor/cfi.c:
Since the mask constant (0x00000080 for the DQ7 mask) shifted in this
case would never have the sign bit set, it worked fine even though it
was accidentally using the SRA opcode instead of SRL.
Change-Id: I0a80746e2075c7df1ce35b9db00d9d0b997a3feb
Signed-off-by: Tobias Diedrich <ranma+openocd@tdiedrich.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/3613
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
We were previously inadvertently clearing the top 32 bits of SCTLR_EL1
during read_memory/write_memory as a result of using 32-bit operations
to access the register and because the fields used to temporarily
store the register were 32-bit. Fix it.
Change-Id: I657d7f949e1f7ab6bf90609e3f91cae09cade31a
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7939
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Associativity=0 means that only one CMO is needed for all ways.
It could also mean that the cache is 1-way, but this is less likely.
Currently Associativity=0 causes us to hang in the while loop in
decode_cache_reg. Fix it by skipping the loop in this case. We can let
way_shift be set to the arbitrary value of 0 because in the case where
Associativity=0 we only ever shift 0 by it before ORing it into the
CMO operand.
Change-Id: I7c1de68d33f6b3ed627cbb1e2401d43185e4c1e3
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7916
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In the unusual (and even incorrect) case of running the command
target create ...
before defining an adapter and the associated transport, the
command causes a segmentation fault. E.g.:
openocd -c 'target create cpu cortex-m -endian little'
Check that get_current_transport() returns a valid pointer before
referencing it.
Change-Id: I9796a7e92196ef3df5c7152b27c34102045dc9e7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7962
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Enhance `mips32_read_config_regs` to better detect MIPS32 ISA,
DSP, and FPU features, allowing user to get more detailed
target information.
Most of these information will be used in MIPS m/iAptiv support.
Change-Id: I23571a626ec64fa019acac91bdbfcb434373bfc1
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7911
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This patch forces a read of register from the target
in the get_reg command in case the register cache
does not hold a valid value at that moment.
Note that the command "reg" already handles it
correctly, no fix is needed there.
Change-Id: I75fad25188e94ee4e06162ab6d600ea24dbf590a
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7958
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Previously, when listing the watchpoints, OpenOCD printed
numbers 0, 1 and 2 representing READ, WRITE and ACCESS type
watchpoints.
This patch changes it to 'r', 'w' and 'a'. This increases the
clarity as what type the watchpoint actually is.
Change-Id: I9eac72dfd0bb2a9596a5b0c080a3f584556ed599
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7909
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
This patch adds the "all" option to the rwp command.
It removes all watchpoints, much like rbp all removes
all breakpoints.
Change-Id: Id58dd103085e558f17afa4a287888cf085566ca9
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7907
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add support for the ARM MCRR/MRRC instructions which require the use of
two registers to transfer a 64-bit co-processor registers. We are going
to use this in a subsequent patch in order to properly dump 64-bit page
table descriptors that exist on ARMv7A with VMSA extensions.
We make use of r0 and r1 to transfer 64-bit quantities to/from DCC.
Change-Id: Ic4975026c1ae4f2853795575ac7701d541248736
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Michael Chalfant <michael.chalfant@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5228
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Currently, instruction cache is being invalidated in
arc_{un,}set_breakpoint() regardless of whether the breakpoint's type is
HW or SW. For SW breakpoints, this has no net effect as the caches are
flushed as a by-product of overwriting instructions in main memory and
is thus merely unnecessary; but for HW breakpoints this invalidation is
not preceded by a flush and might lead to loss of data. This patch
removes the invalidate() call altogether to correct this undesired
behavior for HW breakpoints.
With this patch applied, all supported HW breakpoint tests from the gdb
testsuite are now passing with the arc-openocd backend.
Change-Id: I3d252b97f01f1a1e2bf0eb8fb257bdab0c544bc2
Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7767
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The comment above armv8_dpm_read_current_registers() doesn't match
the implementation, as the function reads all the registers from
ARMV8_PC and above.
The registers currently read are not relevant to answer to the
usual GDB initial request through the 'g' packet. Plus the lack of
differentiation per core state (AArch32 vs AArch64) causes the
read of not existing registers in AArch32 triggering errors, as
tentatively fixed by https://review.openocd.org/5517/
Fix the code to read the registers initially required by GDB.
Modify the comment to report the register list in AArch32 and in
AArch64.
Keep the extra checks inside the read loop, even if they are
mostly irrelevant; this could prevent errors if someone needs to
extend the number of registers to read.
The current implementation of the register's description in
OpenOCD does not allow to discriminate among AArch32 and AArch64
registers. Add a TODO comment to highlight it.
Change-Id: Icd47d93c19a9e1694a7b51bbc5ca7e21a578df41
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7887
Tested-by: jenkins
Previously, if the image file was less than 9 bytes long,
it was assumed to be an error when it could be a binary
image file. This patch makes OpenOCD detect these cases
as binary files.
Change-Id: I5b4dad2b547786246887812ac75907378fe58671
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7880
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This patch unifies the lines printed by the "bp" command
so that different types of breakpoints are printed in
the same format.
Change-Id: Ic1335eda1c58072a334aed9cf0011431c8ec86a4
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7861
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Now internal watch/breakpoint will not be removed in case
of error during removing triggers from hardware.
Also change signature of some functions (for deletion
bp/wp) to print message in case of some error.
Change-Id: I71cd1f556a33975005d0ee372fc384fddfddc3bf
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7738
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Introduce the ability to detect CPUs based on CP0 PRId register and
apply cpu specific quirks, which alter the default ejtag behavior.
First of those is EJTAG_QUIRK_PAD_DRET, which makes sure extra NOPs are
placed after the DRET instruction on exit from debug mode. This fixes
resume behavior on Ingenic JZ4780 SoC.
The proper detection of some (currently unsupported) CPUs becomes quite
complicated, so please consult the following Linux kernel code when
adding new CPUs:
* arch/mips/include/asm/cpu.h
* arch/mips/kernel/cpu-probe.c
Change-Id: I0f413d5096cd43ef346b02cea85024985b7face6
Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7859
Tested-by: jenkins
These cores are advertised as M23 and M33 compatible, but are identified
by the Realtek implementor id. These cores are found on the RTL872xD
family, at least.
Raw CPUIDs:
Real-M200 (KM0): 721cd200
Real-M300 (KM4): 721fd220
Change-Id: I4106ccb7e8c562f98072a71e9e818f57999d664e
Signed-off-by: Karl Palsson <karlp@tweak.au>
Reviewed-on: https://review.openocd.org/c/openocd/+/7846
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Presently, we only look at the Part Number field of the CPUID, and
completely ignore the Implmentor field, simply assuming it to be ARM.
Parts have since been found, with different implementors, that use
overlapping part numbers, causing detection to fail.
Expand the "part number" field to be a full implementor+part number,
excluding the revision/patch fields, to make checking more reliable.
Change-Id: Id81774f829104f57a0c105320d0d2e479fa01522
Signed-off-by: Karl Palsson <karlp@tweak.au>
Reviewed-on: https://review.openocd.org/c/openocd/+/7845
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add missing aarch64_poll() calls to ensure the event
TARGET_EVENT_HALTED is called when necessary.
This is needed with the poller update introduced in commit
95603fae18 ("openocd: revert workarounds for 'expr' syntax change")
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Change-Id: I6e91f1b6bc1f0d16e6f0eb76fc67d20111e3afd2
Reviewed-on: https://review.openocd.org/c/openocd/+/7737
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This patch changes data types of watchpoint value and mask to allow for
64-bit values match that some architectures (like RISCV) allow.
In addition this patch fixes the behavior of watchpoint command to
zero-out mask if only data value is provided.
Change-Id: I3c7ec1630f03ea9534ec34c0ebe99e08ea56e7f0
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7840
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
register_cache_invalidate() is written a way which uses
pointer arithmetic, which makes it harder to read. This patch
replaces it with more readable way to iterate over array of
structs.
Change-Id: Ia420f70a3bb6998c690c8c600c71301dca9f9dbf
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7735
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Lot of messages was logged as LOG_WARNING, but the operation failed
immediately. Sometimes no error message was logged at all.
Add missing messages, change warnings to errors.
Sometimes ERROR_TARGET_INVALID was returned. Some command handlers
returned ERROR_OK! Always return ERROR_TARGET_NOT_HALTED.
While on it use LOG_TARGET_ERROR() whenever possible.
Prefix command_print() message with 'Error:' to get closer
to LOG_TARGET_ERROR() variant.
Error message was not added to get() and set() methods of
struct xxx_reg_type - the return value is properly checked and a message
is logged by the caller in case of ERROR_TARGET_NOT_HALTED.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I2fe4187c6025f0038956ab387edbf3f461c69398
Reviewed-on: https://review.openocd.org/c/openocd/+/7819
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
While not affecting the function's main purpose, an error has
crept into arc_save_context() that results in logging wrong register
values when the debug level is 3 or more. For instance, when debugging a
trivial program and halting at entry to main, the following values are
printed to the log:
Debug: 2915 2020 arc.c:894 arc_save_context(): Get core register regnum=0,
name=r0, value=0x0000000
...
Debug: 2947 2020 arc.c:894 arc_save_context(): Get core register regnum=60,
name=lp_count, value=0x900002d8
Debug: 2948 2020 arc.c:894 arc_save_context(): Get core register regnum=63,
name=pcl, value=0xffffffff
Debug: 2949 2020 arc.c:909 arc_save_context(): Get aux register regnum=64,
name=pc, value=0x900000b4
Debug: 2950 2020 arc.c:909 arc_save_context(): Get aux register regnum=65,
name=lp_start, value=0x900000bc
Debug: 2951 2020 arc.c:909 arc_save_context(): Get aux register regnum=66,
name=lp_end, value=0x00080801
Debug: 2952 2020 arc.c:909 arc_save_context(): Get aux register regnum=67,
name=status32, value=0xffffffff
After the change, the register contents make much more sense:
Debug: 2923 3934 arc.c:889 arc_save_context(): Get core register regnum=0,
name=r0, value=0x00000000
...
Debug: 2955 3934 arc.c:889 arc_save_context(): Get core register regnum=60,
name=lp_count, value=0x00000000
Debug: 2956 3934 arc.c:889 arc_save_context(): Get core register regnum=63,
name=pcl, value=0x900002d8
Debug: 2957 3934 arc.c:903 arc_save_context(): Get aux register regnum=64,
name=pc, value=0x900002da
Debug: 2958 3934 arc.c:903 arc_save_context(): Get aux register regnum=65,
name=lp_start, value=0x900000b4
Debug: 2959 3934 arc.c:903 arc_save_context(): Get aux register regnum=66,
name=lp_end, value=0x900000bc
Debug: 2960 3934 arc.c:903 arc_save_context(): Get aux register regnum=67,
name=status32, value=0x00080801
While at it, simplify a couple of expressions.
Change-Id: I8f2d79404707fbac4503af45b393ea73f91e6beb
Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7765
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Right after target halt, some activities needs to be done
such as printing exception reason, disable wdts and reading
debug stubs information.
Missing activities will be submitted in the next patches.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I27aad5614d903f4bd7c8d6dba6bfb0bdb93ed8dc
Reviewed-on: https://review.openocd.org/c/openocd/+/7757
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
This patch fixes the handling of errno by setting the sys_errn
only if error has actually occurred during the semihosting call.
It also fixes few issues where error was not set in the first place.
Change-Id: I2fbe562f3ec5e6220b800de04cd33aa1f409c7a0
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7730
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
This patch introduces function semihosting_opcode_to_str() which
converts semihosting opcodes to strings. This function is then
used in debug messages to improve log analysis and troubleshooting.
Change-Id: Iffea49dae13d6a626ae0db40d379cba3c9ea5bd3
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7726
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
