* Enforce OpenOCD style guide.
Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8
* Fail if `git diff` fails
Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9
* Maybe every line gets its own shell?
Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6
* Maybe this will error properly.
Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9
* Take different approach than merge-base
Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1
* Fix style issues.
Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
Cortex-M target used 'auto_bp_type' mode. The requested type
of breakpoint was ignored and hard (FPB) breakpoints were set in
'code memory area' 0x00000000-0x1fffffff, soft breakpoints were set above
0x20000000.
The code memory area of Cortex-M does not mean the memory is flash and
vice versa. External flash (parallel or QSPI) is usually mapped above
code memory area. Cortex-M7 ITCM RAM is mapped at 0. Kinetis
has a RAM block under 0x20000000 boundary.
Remove 'auto_bp_type' mode, set breakpoints to requested type.
Change 'cortex_m maskisr auto' handling to use a hard temporary
breakpoint everywhere: it can also workaround not working soft breakpoints
on Cortex-M7 with ICache enabled.
Change-Id: I7a9f9464c5e10bfd7f17cba1037ed07a064fa2e8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4429
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Tested on PSoC6 (Cortex-M0+ core), onboard KitProg2 in CMSIS-DAP mode,
adapter_khz=1000.
Plain read:
flash read_bank 0 /dev/null
takes 48 seconds.
erase_check without this change:
flash erase_check 0
takes horrible 149 seconds!!
And the same command with the change applied takes 1.8 seconds.
Quite a difference.
Remove the erase-value=0 version of algorithm as the new one can check
for any value.
If the target is an insane slow clocked CPU (under 1MHz) algo
timeouts. Blocks checked so far are returned and the next call
uses increased timeout.
Change-Id: Ic0899011256d2114112e67c0b51fab4f6230d9cd
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4298
Tested-by: jenkins
Reviewed-by: Jonas Norling <jonas.norling@cyanconnode.com>
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
'flash erase_check' command runs a check algorithm on a target
if possible. The algorithm is run repeatedly for each flash sector.
Unfortunately every start and stop of the algorithm impose not negligible
overhead.
In practice it means checking is faster than plain read only for
sectors of size approx 4 kByte or bigger. And checking sectors
as short as 512 bytes runs approx 4 times slower than plain read.
The patch changes API call target_blank_check_memory() and related
to take an array of sectors (or arbitrary memory blocks).
Changes in target-specific checking routines are kept minimal.
They use only the first block from the array and process it by
the unchanged algorithm.
default_flash_blank_check() routine repeats target_blank_check_memory()
until all blocks are checked, so it works with both multi-block
and single-block based checkers.
Change-Id: I0e6c60f2d71364c9c07c09416b04de9268807f5e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4297
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
On SMP targets, the "target smp" command creates a list of targets
that belong to the SMP cluster. Free this list when a target gets
destroyed on shutdown. For simplicity, the complete list is free'd as
soon as the first target of the SMP cluster is destroyed instead of
individually removing targets from the list.
Change-Id: Ie217ae1efb2e819c288ff3b1155aeaf0a19b06be
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4481
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
apcsw command was limited to SPROT bit only.
Now user can manipulate any bit except size and addrinc fields.
Can be used e.g. to set bus signal 'cacheable' on Cortex-M7
Change-Id: Ia1c22b208e46d1653136f6faa5a7aaab036de7aa
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4431
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The CTRL/STAT register in the ARM DAP DP has a debug power up
ack bit and a system power up ack bit. Some devices do not set
the system power up ack bit until sometime later. To avoid having
the initial target examination fail due to this or to have a
sticky bit error report claim power failure due to this a user
can now specify that this bit should be ignored.
Change-Id: I2451234bbe904984e29562ef6f616cc6d6f60732
Signed-off-by: Eric Katzfey <eric.katzfey@mentalbee.com>
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3710
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This saves us from re-reading s0 before doing just about anything
program buffer related.
Improves DebugBreakpoint from 3.01s to 2.89s. Feels like the improvement
should be larger than that. Maybe my metric isn't very good.
Change-Id: I85e1a1ddbf09006d76c451a32048be7b773dcfe9
Tim Newsome