Commit Graph

2977 Commits

Author SHA1 Message Date
Tim Newsome d942bce996 Conform to OpenOCD style guide.
Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
2017-12-26 11:38:11 -08:00
Tim Newsome d2c92be73f Merge branch 'master' into update
Change-Id: Icec244b174cc0c67ab58961649a369db7f344824
2017-12-22 13:03:58 -08:00
Tim Newsome 1f66c7827b Fix flash/run algorithm with new register names
Change-Id: I8f539c880ee5da864956f56943411b228d8a5812
2017-12-21 16:41:50 -08:00
Megan Wachs 33ef457c6a Merge pull request #155 from riscv/debug_defines
Update debug_defines to the one used with spike.
2017-12-21 15:17:43 -08:00
Megan Wachs a81ad34af3 Merge pull request #148 from riscv/macbuild
Use %ll instead of %L in scanf.
2017-12-21 15:16:57 -08:00
Tim Newsome 5892b26259 Update debug_defines to the one used with spike.
Change-Id: I627c6ee557d98239227324c33f9b89f6280cbf93
2017-12-21 15:05:12 -08:00
Tim Newsome fa385bdcd5 Use parens after if.
I'm surprised this built with gcc before.

Fixes Issue #150.

Change-Id: I24d2957783c66ad53d5b532a4e930349a2059a97
2017-12-21 12:43:22 -08:00
Tim Newsome 11c261cd50 Add riscv expose_csrs command.
This lets users tell OpenOCD which non-standard CSRs exist on their
target, that will also be accessible and whose existence will be
communicated to gdb.

Change-Id: I56163a9fcb84ad7ebe815ae74fbd9fcc208f5a9d
2017-12-19 10:41:48 -08:00
Tim Newsome 5f86f7208d Hide supervisor registers if there is no S mode.
Also update encoding.h.

Change-Id: I275be7de0aa1af64d13ea191b9f4ff391cfb16dc
2017-12-19 10:41:48 -08:00
Tim Newsome f55d1a2030 Give FPRs ABI names.
Change-Id: If198d10e16671b9868836e23386aaf8d4b05f317
2017-12-19 10:41:48 -08:00
Tim Newsome c7cddd2b5c Remove some debug printfs.
Change-Id: I09989d4c0e102889ecb0eedbd3f4138f8b7bdb8c
2017-12-19 10:41:48 -08:00
Tim Newsome 56ad0e5b30 Avoid another assertion failure.
Change-Id: Ia54f778152974164697b712c360918e17a127d95
2017-12-19 10:41:48 -08:00
Tim Newsome 10c17fdf17 Read misa before using it to check for extensions.
Change-Id: I7a172d83055d8bd833e3349a5b22b47dd5f31f5c
2017-12-19 10:41:48 -08:00
Tim Newsome ec1c814017 Don't rely on hart count until it's correct.
Change-Id: I4e05eb091823b2e0fb481ca0b599072ba1ca70f2
2017-12-19 10:41:48 -08:00
Tim Newsome 46715c7d8a Remove no-longer-true comment.
Change-Id: I888680e73682582438a0de0496238867f1604754
2017-12-19 10:41:48 -08:00
Tim Newsome 120477b2a2 Simplify examine()
Now we don't have to play tricks fooling other parts of our code that
might assert.

Change-Id: Ia574378e1f95ed62d297e6b2e852245e58c9ffc9
2017-12-19 10:41:48 -08:00
Tim Newsome 37278cf2ec Make priv register 8 bits.
(It's really only 2 bits, but something wonky happens between gdb and
OpenOCD if I make it that size.)

Change-Id: I562a65cb0ebe5aa0edcc54c251d0fea0e26f9cb1
2017-12-19 10:41:48 -08:00
Tim Newsome f341db9f72 WIP xml register for 0.11.
On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of
0x40001105.

Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
2017-12-19 10:41:48 -08:00
Tim Newsome 8926e66d3a Hide unknown registers, which probably don't exist
Change-Id: Iffa8fa5ff4b0a01abd30fa302b7087e2011337bf
2017-12-19 10:41:48 -08:00
Tim Newsome 26a54452d2 Fix register names.
Use the ABI ones for every register that we have one for.

Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
2017-12-19 10:41:48 -08:00
Tim Newsome 7c989698a1 WIP better CSR names, and include only existing
Change-Id: I1a234ee07c417ba56da10a61fc2bdbdcc60490a8
2017-12-19 10:41:48 -08:00
Tim Newsome a5cb0b2270 WIP. Hide FPRs if the hart doesn't support F/D.
Change-Id: I988c0c36f2de8157d76874a697b3c054773b787d
2017-12-19 10:41:48 -08:00
Tim Newsome e648856a41 make all debug tests now pass.
Also properly support (I think) D extension on RV32.

Change-Id: I2f0162d36e4c18c251f99b6943403cef30d17d29
2017-12-19 10:41:48 -08:00
Tim Newsome c421fefdcb Checkpoint that seems to work.
Change-Id: I9599aacc256f6340795097732b6f8e8869c2099f
2017-12-19 10:41:48 -08:00
Tim Newsome 1e43d32e01 Use %ll instead of %L instead of scanf.
Mac build barfs on L, and the manpage says they're equivalent.

Hopefully fixes #147

Change-Id: I3aa57775731f3f5ceb03097cae2a9dc6fd426dcd
2017-12-15 15:31:36 -08:00
Tim Newsome 6aff46adcc Fix cut and paste bug.
Now reading 64-bit FPRs on 32-bit harts using scratch memory might work.

Change-Id: Ie8c0fc689386c6e724ecab5e8c855e725fa8dd97
2017-12-14 13:51:13 -08:00
Tomas Vanek 19f8f58c0d target: remove unused event definitions
Events reset-halt-pre, reset-halt-post, reset-wait-pre and
reset-wait-post are not used anywhere.

Change-Id: I9a0f94875b102d9b08f6c2fd9d73a9f05f8e8e79
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4285
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2017-12-12 21:18:10 +00:00
Tim Newsome 0a65a6527d Fix build.
Change-Id: I4e3a36fac77fefa271ae9facbaa990fa330501ae
2017-12-11 12:58:20 -08:00
Tim Newsome e50ee46a6f Merge pull request #131 from riscv/small_progbuf
Support program buffers that are just 2 instructions large
2017-12-11 12:52:31 -08:00
Ake Rehnman 020cb12077 stm8 : new target
New STM8 target based mostly on mips4k. Target communication
through STLINK/SWIM. No flash driver yet but it is still possible
to program flash through load_image command. The usual target debug
methods are implemented.

Change-Id: I7216f231d3ac7c70cae20f1cd8463c2ed864a329
Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com>
Reviewed-on: http://openocd.zylin.com/3953
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-12-07 07:53:13 +00:00
Marc Schink 2fcbe3b8f7 target: Constify parameter of is_armv7m()
Change-Id: Ieea1b0dec88818e9e8d5c8c5d54aa8959556d77b
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4275
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2017-12-06 21:01:19 +00:00
Jonas Norling 7e64451097 adi_v5_swd: Add error message when SWD fails to connect
Error message instead of failing silently.

Change-Id: Ie54a5bf68459d3c0e96cc38080ffad8de0a4b5ce
Signed-off-by: Jonas Norling <jonas.norling@cyanconnode.com>
Reviewed-on: http://openocd.zylin.com/4269
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-12-06 20:55:14 +00:00
Tim Newsome 4d5f74fbe6 Update encoding.h.
Change-Id: Id653500aa525746e8824ff5fd2850c62c8c21c08
2017-11-27 13:23:33 -08:00
Tim Newsome 52cdf286ca Add missing return.
Change-Id: Ida32482903cdfd8eeb043088e84bb1f4f5ac673c
2017-11-16 15:58:08 -08:00
Tim Newsome e28abf7c9e Merge branch 'riscv' into small_progbuf
Change-Id: I1d48cb1f8448ebbf98c8bb369928d1e7a7a78c75
2017-11-01 13:38:17 -07:00
Tim Newsome db754536e8 Support 64-bit FPRs on RV32.
Because there is no instruction that moves just half of a 64-bit FPR
to/from a GPR, we need to use scratch memory for this operation. This
code can theoretically use:
1. DMI_DATA, if it is memory mapped in the target.
2. DMI_PROGBUF, if it is writable in the target.
3. A user-configured address.

I have only tested this code very lightly. One reason is that gdb thinks
that on RV32 harts every register is 32 bits wide. Another is that this
is mostly proof-of-concept to satisfy the small program buffer code
review, which I don't want to drag out forever.

Existing tests don't realize that floating support was broken with
RV32D, and don't realize that it still doesn't work because of the gdb
problem mentioned above.

This change improves Issue #110 but there's more work to be done.

Change-Id: I99b8a36e5fea26f1d9e16e36cf99adc7be26b944
2017-10-27 13:15:22 -07:00
Christopher Head bca67d107f Cortex-M: Delete an unnecessary local variable
The dhcsr_save variable was used to save the value of
cortex_m->dcb_dhcsr so it could be restored later. However, all writes
in between the save and the restore use mem_ap_write_atomic_u32, not
cortex_m_write_debug_halt_mask, which means cortex_m->dcb_dhcsr isn’t
changed anyway. Delete the unnecessary local.

Change-Id: I064a3134e21398e1ecfc9f1fa7efd7b020b52341
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4240
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-10-27 11:47:22 +01:00
Christopher Head 02df0abb54 Cortex-M: fix stale DHCSR cache values
In cortex_m_assert_reset, in two locations, DHCSR is written directly
using mem_ap_write_u32. This means that the cached version,
target_to_cm(target)->dcb_dhcsr, is not updated when these writes are
performed, so subsequent writes to DHCSR that use
cortex_m_write_debug_halt_mask will change those bits back to their old
values which, unless modified in that particular invocation, come from
the cache. This causes an actual, observable bug on an STM32F7 in which
running “reset run” immediately after “program” can in some cases result
in execution proceeding with C_MASKINTS set (it is cleared on line 1021
but is then set immediately afterward in cortex_m_clear_halt), causing
failure of the application. Replace these mem_ap_write_u32 calls with
cortex_m_write_debug_halt_mask calls to do the same jobs.

Change-Id: Id35ca7f6057c2df2ba9cd67c53a73b50816d0b71
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4239
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-10-27 11:47:16 +01:00
Tim Newsome 1acb128290 Remove unused variables.
Change-Id: I678d0a65c22792895375dc6916381f81af8f83e4
2017-10-25 13:37:56 -07:00
Tim Newsome 23bd6d08c9 Remove more unused functionality.
Change-Id: I43283b9556c959f891a587fb39bdd1ab9206e8af
2017-10-24 15:11:33 -07:00
Tim Newsome dbecbfee99 Add a fence after memory writes.
Change-Id: I5137479b685f735aa573cec5d40170016c40f597
2017-10-24 12:15:25 -07:00
Tim Newsome 59a0340261 Remove more unused code.
Change-Id: I962660f58d948f85df6e073065e15e5d8f4a02b6
2017-10-24 11:38:39 -07:00
Tim Newsome 8432b7cf3d Remove more unused code.
Change-Id: Id91237c163d86e8f4d039503ca33b4ad7571ecd1
2017-10-24 11:34:48 -07:00
Tim Newsome 3ba6d46fc2 Remove unused functionality.
Change-Id: Ic70cebd62bbd04f7ae5566504fbb279a11de57f0
2017-10-23 14:45:58 -07:00
Tim Newsome 5425c871c9 Properly fix memory read when encountering busy.
Change-Id: I377054495e860076edc2f38d1cc0f11c23f98d3b
2017-10-23 14:13:46 -07:00
Freddie Chopin 079d78f7de Fix GCC7 warnings about string truncation
GCC7 with -Wall warns about possible string truncation with
snprint()-type functions with "directive output may be truncated writing
1 byte into a region of size between 0 and 9
[-Werror=format-truncation=]" + "note: ‘snprintf’ output between 5 and
14 bytes into a destination of size 12" (or similar). Fix this by
increasing sizes of buffers.

See https://gcc.gnu.org/gcc-7/changes.html

Change-Id: Ib848f2a56dd658783534158947ae1be7c0e99d45
Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-on: http://openocd.zylin.com/4175
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2017-10-23 10:54:24 +01:00
Freddie Chopin 9364b0dba4 Fix GCC7 warnings about switch-case fallthroughs
GCC7 with -Wextra warns about switch-case blocks which fallthrough with
"this statement may fall through [-Werror=implicit-fallthrough=]". This
can be fixed by adding "special" comments: "/* fallthrough */".

See https://gcc.gnu.org/gcc-7/changes.html

Change-Id: Iba0be791dbdd86984489b2d9a0592bb59828da1e
Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-on: http://openocd.zylin.com/4174
Tested-by: jenkins
2017-10-23 10:54:16 +01:00
Andreas Fritiofson ef49b34b2a arm: semihosting: set command line arguments
Add "arm semihosting_cmdline [argv0 argv1 ...]" for setting the
command line arguments for the debuggee.

[andreas.fritiofson@gmail.com]: Dynamic allocation, empty default

Change-Id: I831ddd161d602f251940e29608a154e9590fdee1
Signed-off-by: Christian Groessler <chris@groessler.org>
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3106
Tested-by: jenkins
2017-10-22 23:06:09 +01:00
Tim Newsome a3a137062d Pay attention to impebreak.
This required updating debug_defines.h, which caused a few other small
cleanups as well.

Change-Id: I3c2cb418d7eff3093d7664c5563b2af5e8b530eb
2017-10-18 14:21:23 -07:00
Tim Newsome 85bfab36ad Remove unused functionality.
Change-Id: I0c1464e2e6aa12d0cb1025ed0a7c1c483e7403b7
2017-10-18 12:47:07 -07:00