added an alternative way to enter debug mode, which does not require restarting the chip.
this will not always work, but in general it will (failure 0.3%), and failure is not a dramatic issue, simply have to use the full sequence.
the user can only access "halt", which uses the full sequence, so the user should not have any problems.
restarting the chip requires reconfiguring the flash module. the doc is very poor, so i'd rather have the two methods, and live with the 0.3%.
sometimes the master tap will be enabled, since tap switching is required during halt/lock/unlocking procedures.
now irscan handles this, avoiding unnecessary warnings and preventing errors.
got new info regarding setting the chip to debug mode, and locking/unlocking flash memory.
the newer implementation is a bit slower, but always works.
the previous implementation would randomly (as once every 25k-70k times) get the chip into a state where the freescale tool would be necessary. this is fixed now.
added functions to play around with the jtag state machine. they are not the happiest, but are necessary to be able to execute the halting/locking/unlocking sequences.
Conflicts:
src/target/dsp5680xx.c
the user can execute halt, but no enter_debug_mode. modified the error handling to suite this.
the new implementation of unlocking will use enter_debug_mode, and should not get the same errors as the user would, because not being able to enter debug mode is actually success when checking for locked flash.
crc check was always performed on newly flashed data, now it is optional
flash mem can be locked by writing a specific word to a specific address in flash.
to verify flash, target must be halted, and this will (when the new halt sequence is implemented) require reseting the chip. if the target is reset after writing the lock words, then it will lock, hence the CRC will fail because it is not possible to read stuff from the target.
also added a function that resets the jtag state machine.
this is not used yet, but will be soon.
it is implemented to allow strict control over JTAG state machine, necessary to implement to halt and unlocking sequences.
Due to build warnings introduced in newer versions of ftd2xx we
use strings to report errors rather than result codes. This also
gives us the same behaviour as libftdi.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Scripts sourced via 'script' should evaluate in the global
scope to make it easy to set and reference global variables.
Signed-off-by: Steve Bennett <steveb@workware.net.au>
i had started my code from dsp5683xx, i renamed a bunch of stuff to names i consider to be better.
i believe no one is using this code, so nobody should be affected. (it's not too late to do this change)
After correcting the reply size counter, it should be safe to rely on it
for the number of bytes expected in the USB read, instead of reading the
endpoint maximum. This doesn't make things go any faster but it's nicer and
removes the local buffer.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Add a helper function for running the queue if it would overflow otherwise.
Use it to simplify the queue fill level checks and optimize in a few cases
that would previously run the queue prematurely.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
After the reply_index handling is fixed, there's no need to special case
the out scan.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
dtc_queue.reply_index was wrongly being increased during out scans, causing
the queue to be sent before the out buffer was full. This patch increases
raw upload speed by 50% or so.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Indentation was inconsistent and some lines not indented at all. Quickfix
using Eclipse's auto-indentation.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Function mips_m4k_write_memory() does endianess byte swap,
but this procedure break one byte access (temporary array
overwrites content in buffer).
As a fix, this endianess swap and buffer affecting
is preformed only on hword and word accesses (not on byte access).
Pprogram that loads another program into memory is actually writing the
D- side cache.
The instructions it has loaded can't be executed until they reach the
I-cache.
After the instructions have been written, the loader should arrange to
write back any containing D-cache line and invalidate any locations
already in the I-cache.
For the MIPS Architecture Release2 cores, we can use synci command
that does this job.
For Release1 we must use "cache" instruction.
This patch adds MIPS32 CP0 coprocessor R/W routines,
as well as adequate commands to use these routines via
telnet interface.
Now is becomes possible to affect CP0 internal registers
and configure CPU directly from OpenOCD.
For all architectures we use distinct common magic number,
and this should be a uint32_t type.
Otherwise, comparison with macros will yield compilation
warning.
