c534a37fc3
Make reset work again for multicore
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Both regular multicore and RTOS hack methods.
Change-Id: I9a0998de0f33ef8a4d163f36ddf01c7675893b3d
2018-03-23 12:53:24 -07:00
d7282d0bfe
Add set_supports_havereset
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This lets reset work on targets that don't implement havereset.
Change-Id: I09eb20970fac740eb6465541db6e739ae3e6b0d5
2018-03-22 12:44:15 -07:00
e5591c2584
Halt the target again if it was reset while halted
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Change-Id: I59707e7b2e1646c312d4eb8e96e9d7dfd1e128c2
2018-03-20 12:34:17 -07:00
40e0c5b976
Format error messages.
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Change-Id: I50c21319765e1ead279223466ed02a06ecf6a522
2018-03-19 12:46:10 -07:00
4d2d1f7324
Notice when a hart has reset.
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Attempt to notify the user.
Deal correctly with a halted target that is suddenly running.
Change-Id: Ib0e0aa843d1da22df673713687ec884f6af14949
2018-03-16 15:04:14 -07:00
fd2759a63d
Clear havereset in examine() and deassert_reset().
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Change-Id: I89f32a44ebd6f3df0d0e2f6b54b111daa6ab06f7
2018-03-16 15:03:31 -07:00
848062d0d1
Propagate errors in more places
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Change-Id: I5a7594d4b44c524537827f403348d0c10814546f
2018-03-16 15:03:31 -07:00
3ddbbd525d
Merge pull request #222 from riscv/dmi_commands
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Add riscv dmi_read/dmi_write commands.
2018-03-15 11:32:33 -07:00
fd9de02fac
Merge pull request #221 from riscv/reg_running
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Error instead of asserting on reg access failure
2018-03-07 12:22:33 -08:00
c10c570dca
Fix cut and paste error message.
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Change-Id: I1ff28278c6fc1b6dda1be53ca4f8ec2dd841b117
2018-03-06 13:22:57 -08:00
ddb894edf6
Add riscv dmi_read/dmi_write commands.
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Mostly addresses #207 .
Also changed dmi_read() to return an error, and fixed all the call sites
to propagate that error if possible.
Change-Id: Ie6fd1f9e7eb46ff92cdb5021a7311ea7334904f1
2018-03-06 12:45:55 -08:00
509e0e4715
Error instead of asserting on reg access failure
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Instead of asserting, return error when an abstract register access
fails on running target.
Fixes #201
Change-Id: I1ab3b31b0a4babf83c44f95ee2eeca92ef906d2f
2018-03-02 20:24:58 -08:00
84c0fdd5d1
Don't always error if a debug program fails
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This is often expected, and the calling code should decide whether to
emit an error or not.
Change-Id: Ic21f38b4c75f01e6b40034fdc60dde6ba7a55f4a
2018-03-02 20:02:32 -08:00
1d00d03dc0
Remove unable to read register error message
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It confuses users of IDEs like Eclipse, which request to read registers
that don't exist on the target.
Fixes #176
Change-Id: Ie2504140bfc70eba0d88fd763aacd87895aa20ff
2018-03-02 19:41:31 -08:00
1d9418fbb0
Only propagate register errors on some targets
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Without this change, connecting to ARM targets is impossible.
Fixes #115 .
Change-Id: Ie33c7e15ac1bed8c9cbd8e6a78de92d5498c5999
2018-03-01 15:11:11 -08:00
0c8235d11f
Merge pull request #216 from kaspar030/fix_some_fallthroughs
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target/riscv: add some switch fallthrough comments
2018-02-28 12:31:22 -08:00
d388f1cbb2
Merge pull request #218 from riscv/auth
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Add `riscv authdata_read` and `riscv authdata_write` commands to support arbitrary authentication through TCL scripts
2018-02-28 09:20:31 -08:00
39716b15ab
Fix authentication for multi-core targets.
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When authdata_write sets the authenticated bit, examine() every OpenOCD
target that is connected to the DM that we were authenticated to.
Change-Id: I542a1e141e2bd23d085e507069a6767e66a196cd
2018-02-27 14:22:06 -08:00
10108b623d
Add authdata_read and authdata_write commands.
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They can be used to authenticate to a Debug Module.
There's a bit of a chicken and egg problem here, because the RISCV
commands aren't available until the target is initialized, but
initialization involves examine(), which can't interact with the target
until authentication has happened. So to use this you run `init`, which
will print out an error, and then run the `riscv authdata_read` and
`riscv authdata_write` commands. When authdata_write() notices that the
authenticated bit went high, it will call examine() again.
Example usage (very simple challenge-response protocol):
```
init
set challenge [ocd_riscv authdata_read]
riscv authdata_write [expr $challenge + 1]
reset halt
```
Change-Id: Id9ead00a7eca111e5ec879c4af4586c30af51f4d
2018-02-27 09:27:00 -08:00
9033d99491
Merge pull request #217 from riscv/disable_target64
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build with --disable-target64
2018-02-26 12:06:47 -08:00
3c1c6e059c
Merge pull request #203 from riscv/sysbusbits
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Add support for system bus master, and for targets that don't have any program buffer
2018-02-20 09:22:22 -08:00
d570f89303
target/riscv: add some switch fallthrough comments
2018-02-20 14:31:31 +01:00
6b02ab4196
Fix build with --disable-target64
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Change-Id: I5acf47845ff197a1aeb31356de7e4cd8ce63d476
2018-02-19 15:07:10 -08:00
352e6b82ed
Merge pull request #208 from riscv/run_from_trigger
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Handle resuming from a trigger...
2018-02-19 13:42:50 -08:00
5c543ee3a1
complete reset before writing to hartsel field
2018-02-07 16:06:02 -08:00
ace6b7e49a
Handle resuming from a trigger...
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... by disabling all triggers, single stepping, enabling them, and then
resuming as usual. Without this change, you'd just be stuck on an
address trigger and would have to manually disable it.
Change-Id: I5834984671baa6b64f72e533c4aa94555c64617e
2018-02-07 13:30:23 -08:00
a80ab87efd
Add unreachable return for mingw build.
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Change-Id: I8c0c4d7be8f6f28638cc2b5ae8114f5c8f95f94b
2018-01-31 16:55:43 -08:00
7114ef485c
Fix cut and paste bug.
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Change-Id: I1c554cbe3d7cb7845bc62f14ae6b8dff107eb192
2018-01-31 16:45:33 -08:00
bb2c25c5ce
Make OpenOCD work when there is no program buffer.
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Fixed abstract register access for registers that aren't XLEN wide.
Avoided excessive errors cases where we attempted to execute a fence but
failed.
Don't mark all the CSRs as caller-save. gdb was saving/restoring
dscratch, which broke function calls as a side effect. dscratch is
accessible for people who really know what they're doing, but gdb should
never quietly access it. The same is probably true for other CSRs.
Change-Id: I7bcdbbcb7e3c22ad92cbc205bf537c1fe548b160
2018-01-31 15:33:45 -08:00
6f0d70f5c8
Mention register name instead of number in error
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Change-Id: I5be5e57418e672fc76383fc24635cdbfb1e65578
2018-01-30 12:30:39 -08:00
ee93a9b2f1
Add error handling code to system bus read/write
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It's not tested because spike never reports any busy errors since every
access happens instantaneously.
Change-Id: If43ea233a99f98cd419701dc98f0f4a62aa866eb
2018-01-30 08:53:46 -08:00
0f0c5b1ff5
Merge branch 'riscv' into sysbusbits
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Change-Id: Ib7921c73a4bdd586703031be3509d1dec9bb3913
2018-01-29 11:39:14 -08:00
6a98fb7076
Detect hartsellen, limiting which harts we probe
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Tested with doctored spike with hartsellens of 0, 1, 3, and 10.
Change-Id: I97f57c7d03b076792d5ecd66545d9b9e853ed515
2018-01-26 16:39:58 -08:00
5184c32125
Clear errors that we see.
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Also WIP towards handling busy errors, but I'm putting that on hold
while I change the spec...
Change-Id: Iccf47048da46e75b0d769e56004fd783bba1dbf0
2018-01-26 15:43:05 -08:00
b67379700b
Add support for v1 system bus access.
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This is functional, but doesn't handle errors.
Change-Id: Ifb46af1b0b567f3c2a6135b2ad5eb7ba63a3f595
2018-01-26 15:43:05 -08:00
beac00149c
Use new debug_defines.h
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Change-Id: Iefc8424343dbed05fa9dacc626829955fc16f299
2018-01-26 15:41:45 -08:00
2d263bae84
Make all memory logging lines consistent.
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Also reduce a few 64-bit variables to 32 bits, which is all they need.
Change-Id: I23e431b7eed4a63803add93a1bb328a3631631d6
2018-01-24 13:53:11 -08:00
42e601afc1
Merge pull request #191 from riscv/scanbuild
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Fix some niggles found by clang's static analysis.
2018-01-24 07:59:47 -08:00
553a63808c
Fix some niggles found by clang's static analysis.
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Change-Id: Id476227e1bd02e067f0cc4da9bc7ffb3d9d30535
2018-01-23 15:16:23 -08:00
3839cbf0ad
Add some error checking to examine().
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Fixes #183 .
Change-Id: I6fb45adf4c97ea339c9d4ca3b372a09b18e3b56e
2018-01-19 13:58:02 -08:00
7f368468c8
Remove dead code.
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Change-Id: Ic90598b3dd4128dabb18ac4dc1285ca721a6a441
2018-01-15 12:07:20 -08:00
6f9585068f
Merge pull request #172 from riscv/dbus_read_comment
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Add a comment in dbus_read
2018-01-10 15:30:56 -08:00
0d60a29c21
Merge pull request #178 from riscv/cleanup
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Rename dummy variable to be correct.
2018-01-10 15:16:40 -08:00
29c7a76708
Muck with mstatus to always be able to read FPRs
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Change-Id: I7ff8bde4578c9ddd175c5cca370295c790cfbba7
2018-01-09 12:06:11 -08:00
fd506fa839
Propagate register read errors.
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Change-Id: Idda111377873a2236b5b91e4ffdabd2be384b47a
2018-01-08 11:53:02 -08:00
0e3869cbf6
Merge pull request #179 from riscv/multicore_hart_selection
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Select current hart before reading memory.
2018-01-05 14:07:38 -08:00
11e51af3b1
Merge pull request #173 from riscv/warn_names
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Use register names instead of numbers in warnings
2018-01-05 13:07:08 -08:00
37434ffd77
Rename dummy variable to be correct.
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Change-Id: I329404894227bb3cf563382e1adf0edda702543b
2018-01-05 13:05:33 -08:00
6f3913cedc
Select current hart before reading memory.
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This avoids trying to read memory from the wrong hart, if the current
hart was changed by an earlier call (eg. to poll()).
Change-Id: I73da1e01c8d01d68f01ac7fdd6c548380a70cfd3
2018-01-04 17:12:01 -08:00
097d62d159
Make delay update messages debug instead of info.
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They confuse users otherwise.
Change-Id: I3bc491352f5384e36c54696a0ecbf11ac623dd83
2018-01-04 13:36:53 -08:00
Tim Newsome