This adds the ATmega256RFR2 to the list of know devices for flashing.
Change-Id: Ib24a508762aaa84ba08ba37409db2ae674b46288
Signed-off-by: Lars Pöschel <poeschell+openocd@mailbox.org>
Reviewed-on: http://openocd.zylin.com/5504
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The current method used for flash addressing uses 16 bit. Every access
to flash is 16 bit wide. With 16 address bits one can address 0x10000
unique locations á 16 bits thats 0x20000 bytes.
For flashes bigger than that avrs have an extended addressing with more
than 16 address bits. This is now implemented and used for flashs larger
than 0x20000 bytes.
Change-Id: Id8b6337dde3830fb3c56b9042872e040bb67c12d
Signed-off-by: Lars Pöschel <poeschell+openocd@mailbox.org>
Reviewed-on: http://openocd.zylin.com/5502
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
STM32WB3x devices' flash are quite similar to STM32WB5x,
except the maximum flash size, which is 512K for WB3x and 1M for WB5x
Change-Id: I3098d7153a7429e0e72c75cec962c05768b0b018
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5475
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
STM32WLEx devices are based on arm Cortex-M4 running at 48MHz,
contains a single bank of maximum 256 Kbytes of flash memory.
there is 3 variants with different Flash/RAM sizes:
STM32WLE5JC : 256K/64K
STM32WLE5JB : 128K/48K
STM32WLE5J8 : 64K/20K
the work-area size is set to 20 kb to fit in STM32WLE5J8
Change-Id: Ie8e186fe4be97cbc25c53ef0ade4b4dbbcee6f66
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5450
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
+ minor changes in comments' alignment to please our eyes
Change-Id: Ifa35a1032afc4e9aee524f596c0298a9eea49c37
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5500
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
STM32G0 and G4 uses the same flash driver as the stm32l4x
Change-Id: Ic1c4be70aaee809536912e0390f07893efb9a082
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5482
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Flash module of STM32G0/G4 family is quite similar to the one of
STM32L4, so only minor changes are required, in particular
adaption of flash loader to Cortex-M0. Register addresses
passed to flash loader to simplify integration of L5.
Added re-probe after option byte load.
Added flash size override via cfg file.
WRPxxR mask now based on max. number of pages instead of fixed 0xFF,
as G4 devices fill up unused bits with '1'.
Sizes in stm32l4_probe changed to multiples of 1kB.
Tested with Nucleo-G071RB, G030J6, Nucleo-G431RB and Nucleo-G474RE.
Gap handling in G4 Cat. 3 dual bank mode tested with STM32G473RB.
This handling isn't optimal as the bank size includes the
size of the gap. WB not tested.
Change-Id: I24df7c065afeb71c11c7e96de4aa9fdb91845593
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4807
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Added fixes for issues found in additional code reviews.
Fixed host Endianness issues with using buffer reads
and writes instead of the *_u32 variants.
Changed code that tried to ID banks by hardcode
bank_number values to use instead the bank base
address. This fixes problems using configurations
with multiple devices.
Note that this replaces Change 4786 which has
been abandoned because of extensive changes to
the code to stop IDing banks by name. And I
think I really messed up a rebase/merge on the
document file.
Tested on MSP432P401R, MSP432P4111, and MSP432E401Y
Launchpads.
Change-Id: Id05798b3aa78ae5cbe725ee762a164d673ee5767
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5481
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Adopted only fast algorithm for flash programming:
- write_word and write_byte methods have been removed.
- start and end write alignments have been defined.
Moved flash controller registers offsets in a common file
shared with the flash algorithm.
- the flash base address is passed to the flash algorithm
as a parameter.
Removed unused functions
Change-Id: I80aeab3994e477044bbcf02e66d9525dae0cb491
Signed-off-by: luca vinci <luca.vinci@st.com>
Reviewed-on: http://openocd.zylin.com/5393
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Michele Sardo <msmttchr@gmail.com>
Writing bits to an uninitialized buffer generated false warnings.
Zero buffers before setting them by buf_set_u32|64()
(do it only if bit-by-bit copy loop is used,
zeroed buffer is not necessary if a fast path write is used)
Change-Id: I2f7f8ddb45b0cbd08d3e249534fc51f4b5cc6694
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5383
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The aligning code generated a clang static analyzer warning and
imposed huge memory leak. This part of code was removed and
flash infrastructure to alignment is used instead.
Not tested on hw!
Change-Id: I7c71da87547e71d595a7e7071ae5adcc1cecc827
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5367
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
this new device has the following features:
- single core cortex-M7
- 2MB flash - dual bank
- page size 8k
- write protection grouped by 4 sectors
- write block size 128 bits (16 bytes)
the bit definition of FLASH_CR is different than STM32H74x,
that's why we introduced a helper to compute the FLASH_CR value
Change-Id: I4da10cde8dd215b1b0f2645f0efdba9d198038d1
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5441
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The script checkpatch available in new Linux kernel offers an
experimental feature for automatically fix the code in place.
While still experimental, the feature works quite well for simple
fixes, like spacing.
This patch has been created automatically with the script under
review for inclusion in OpenOCD, using the command
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types POINTER_LOCATION --fix-inplace -f {} \;
then manually reviewed.
OpenOCD coding style does not mention the space around pointer's
asterisk, so no check is enforced. This patch only makes the style
uniform across the files.
The patch only changes amount and position of whitespace, thus
the following commands show empty diff
git diff -w
git log -w -p
git log -w --stat
Change-Id: Iefb4998e69bebdfe0d1ae65cadfc8d2c4f166d13
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5197
Tested-by: jenkins
Report the 32-byte alignemnt requirement via the bank structure rather
than enforcing it ad-hoc in the write routine. This allows people to do
non-32-byte-aligned writes if they want, with the infrastructure fixing
up the addresses passed to the low-level driver.
Change-Id: I2c4f532f2000435954a900224dbc9f2c30d1cc94
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5388
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Without this, a failed attempt to change option bytes will silently
appear to succeed but without actually changing the option bytes
(confusingly, the option bytes will still read back as if they had been
changed until a reboot as well!).
Change-Id: Id529c6c384a8a16be75f5702310670d99d8fac79
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5418
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
We have the macro ARRAY_SIZE() already available. Use it!
Issue identified by checkpatch script from Linux kernel v5.1 using
the command
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types ARRAY_SIZE -f {} \;
Change-Id: Ic7da9b710edf118eacb08f9e222f34208c580842
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5198
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
this is to avoid confusion with STM32 L4, L4+ and L5 families
also:
- a warning message is changed to error
- stm32l0x and stm32l1x aliases has been created to permit
the usage of either names
Change-Id: If3f16d2a3b7d1369959aa7407da37a9076ea91d7
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5437
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This will enable us to use either name when calling flash driver commands.
For example the stm32wbx family use the same flash driver as the stm32l4x, so
the user has to use 'stm32l4x lock 0' which can be confusing.
Now the user can also use 'stm32wbx lock 0' with the same result.
Change-Id: Ic0d8da9afc202d7cc82d9b9949827e958a1cc824
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5436
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add driver for the RPC block in HF mode on Renesas R-Car Gen3 SoCs.
This driver allows operating the on-SIP HF memory.
Note that HF is CFI compliant flash, but it is not memory mapped,
hence the need to replace all the memory accessors and read/write
functions. The write function is entirely replaced to increase
performance and is Spansion/AMD specific, since there is no known
SIP with other HF from another vendor.
Add the following two lines to board TCL file to bind the driver on
R-Car Gen3 SoC using HyperFlash:
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME rpchf 0x08000000 0x4000000 2 2 $_CHIPNAME.a57.0
Change-Id: Ie18729d017eeb46e1363333ffe002d010dfc5ead
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5149
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Fix comment of tested errors in asm src.
List all relevant errors in FLASH_ERROR mask: FLASH_PROGERR was missing
and any trial to re-program already programmed double word ended up
in the error bit held uncleared and flash write permanetly repeating
the error message until reset.
Lock the bank also after unsuccesfull write_block run.
Set async target algo block size to size of double word.
Remove warning in case of write_block success. In case of error
use LOG_ERROR instead of warning.
Change-Id: Ibf6d5e306a4c2eaa43de67d636b4902c737f02f3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5360
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
The original code paded the write chunk with random bytes by overrunning
the buffer. An user can easily regard the random bytes to
be a programming error.
Change-Id: Ib0f47b5bc406bc6a7c32f3d929bf324a17c7c1e1
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5359
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
The chip->hwid is uint32_t , fix the print format.
This was detected by TravisCI on OSX, where this triggers a build error.
Change-Id: I776a7bb50e396c8fccc24500dec4750190da7982
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5401
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Ilya Kharin <akscram@gmail.com>
Add driver for the SH QSPI controller. This SPI controller is often
connected to the boot SPI NOR flash on R-Car Gen2 platforms.
Add the following two lines to board TCL file to bind the driver on
R-Car Gen2 SoC and make SRAM work area available:
flash bank flash0 sh_qspi 0xe6b10000 0 0 0 ${_TARGETNAME}0 cs0
${_TARGETNAME}0 configure -work-area-phys 0xe6300000 -work-area-virt 0xe6300000 -work-area-size 0x10000 -work-area-backup 0
To install mainline U-Boot on the board, use the following procedure:
proc update_uboot {} {
# SPL
flash erase_sector 0 0x0 0x0
flash write_bank 0 /u-boot/spl/u-boot-spl.bin 0x0
# U-Boot
flash erase_sector 0 0x5 0x6
flash write_bank 0 /u-boot/u-boot.img 0x140000
}
Change-Id: Ief22f61e93bcabae37f6e371156dece6c4be3459
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
---
V2: - Add Makefile and linker script for the SH QSPI IO algorithm
- Include the algorithm code instead of hard-coding it
Reviewed-on: http://openocd.zylin.com/5143
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This is a preparatory change, align the function name with the rest
of the API, no functional change.
Change-Id: I6a810d2a54edcd13ad9a87d24a7334802c41623b
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5391
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This is a preparatory change, align the function name with the rest
of the API, no functional change.
Change-Id: Ib967520f027b03eb1792b36ede52335df8e23941
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5390
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add possibility to supply custom CFI memory accessors via cfi_info
and override the default memory-mapped ones.
Change-Id: I1b6bc1db69fc33e8cdef96c41742c40e6d8917e9
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5147
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The size argument is always set to bank->bus_width and bank pointer
is now passed into cfi_target_{read,write}_memory(), so the size
can be accessed through the bank pointer inside the function instead
of being explicitly passed in.
Change-Id: I0abc1cc3bf513281c10cb5de7a21cb0e75cb7676
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5389
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Replace passing in struct target with passing in struct flash_bank,
so that the later can contain function pointers to custom per-driver
memory accessor functions.
Change-Id: Id2573a6d5f1a73ed9c4f73c53592a9a335a11c99
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5146
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
STM32L4P/Q devices have:
- similar flash layout as STM32L4R/S devices
- 1024K of flash memory (some parts have 512K only)
tested on NUCLEO-L4P5ZG using board/st_nucleo_l4.cfg
Change-Id: I77047351bc7dcd7c76d0f31a77be73005104a06f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5392
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This rework is inspired from the 'flash/nor/stm32h7x.c'
This rework will ease the support of new devices on top of this driver:
for example: STM32WB have different flash base and size addresses
Notes:
- stm32l4_probe modified in order to charge the correct part_info from
the defined stm32l4_parts according to the device id
- stm32l4_flash_bank.bank2_start is replaced by .part_info->bank1_sectors
- STM32_FLASH_BASE is removed , part_info->flash_regs_base will be used instead
based on that flash register addresses are changed to offsets,
>> stm32l4_get_flash_reg was modified accordingly
- stm32l4_read_option and stm32l4_write_option was modified to accept an
offset instead of an absolute address, luckily this is the commands'
argument by default
- stm32l4_mass_erase modifications :
- use MER2 only on top of dual bank devices
- wait for BUSY bit before starting the mass erase
Change-Id: Ib35bfc3cbadc76bbeaaaba9005b82077b9e1e744
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/4932
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Create separate memory read/write functions which facilitate access
to the CFI NOR, so that they can be replaced by controller-specific
functions if necessary. This would become necessary when implementing
support for e.g. HyperFlash controllers, which do not directly map
the HyperFlash into the address space.
Change-Id: I1bba1edfd397cb37bfedb43efe2dd03feb26a375
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5145
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Factor out the spansion unlock sequence to deduplicate the code.
Change-Id: Id78522e9a2f0e701870ef816772289d08257476a
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5144
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
