Commit Graph

3 Commits

Author SHA1 Message Date
Antonio Borneo
eef37df3aa target: cortex-m: defer cache identification on Cortex-M7 under reset
On Cortex-M7 only, several registers in System Control Space (SCS)
are not accessible when the CPU is under reset, generating a bus
error.
This causes OpenOCD to fail examining the CPU when the board reset
button is pressed or when the flag 'connect_assert_srst' is used
on 'reset_config' command.

Introduce a deferred identification of the cache and run it during
polling and at target halted (just in case of polling disabled).

Change-Id: Ia5c582ae95f825c5fb8c2dcfb320142f7ac04a9f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9232
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-11-30 10:22:07 +00:00
Antonio Borneo
88b9bd396d target: cortex-m: fix support for armv8m caches
Scan-build is unable to correctly follow the deferred loading of
queued read, finalized by the atomic write, thus it incorrectly
claims that the arrays d_u_ccsidr[] and i_ccsidr[] could carry
not initialized values:

	armv7m_cache.c:154:31: warning: 1st function call argument
	is an uninitialized value [core.CallAndMessage]
	   cache->arch[cl].d_u_size = decode_ccsidr(d_u_ccsidr[cl]);

	armv7m_cache.c:172:29: warning: 1st function call argument
	is an uninitialized value [core.CallAndMessage]
	   cache->arch[cl].i_size = decode_ccsidr(i_ccsidr[cl]);

Initialize the arrays to zero to hide these false positive.

Change-Id: I6d1e88093cb8807848643139647a571c1b566aa8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 04da6e2c62 ("target: cortex-m: add support for armv8m caches")
Reviewed-on: https://review.openocd.org/c/openocd/+/9167
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-10-18 08:59:44 +00:00
Antonio Borneo
04da6e2c62 target: cortex-m: add support for armv8m caches
Cores like Cortex-M7, Cortex-M55 and Cortex-M85 can have either
D-Cache and/or I-Cache.
Using SW breakpoints in RAM requires handling these caches.

Detect the presence of cache at examine.
Detect cache state (enable/disable) at debug entry.
Take care of caches synchronization through the PoC (usually the
SRAM) while setting and removing SW breakpoints.
Add command 'cache_info' to check cache presence and size.

Change-Id: Ice637c215fe3042c8fff57edefbab1b86515ef4b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9077
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2025-10-11 15:56:41 +00:00