Implement it as a function, the code was already in. Added optimize
option.
Change-Id: Ib9ad3f00d6c4f0b91c4e4960a50ec8d102f4e333
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4017
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
In most of the cases there is no need to request execution,
the check for a new pracc access already does it.
Requesting execution if not needed makes execution slower and
code larger due the additional checks.
Reduce code in fasdata transfer function.
Call for execution when exiting debug.
Change-Id: I3b45f6d1f62da5fad3e3db84f82a9299b16e1bd9
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4010
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Struct mips32_pracc_context no more in use.
In current code cp0 reg/sel do not requires special handling.
In sync mode ctx.store_count not used, drop check.
In fasdata transfer function use mips32_pracc_read_ctrl_addr()
to reduce code.
Change-Id: Ibd4cfa5a44ebc106ed0db042f4e54a2e0b3d43cb
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4007
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Will be used later, allow queuing all needed scans in a pracc
access. This makes faster execution with ftdi based adapters
working in sync with pracc.
Added now because the overall code is shorter.
Change-Id: Ib32b89307b75785f88870db8d7c9255dc5bbd426
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4005
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The halt event was left pending in the CTI, better to clear it immediately
after debug entry.
Change-Id: I6002f862681baf98769e3c73332a7f7f0ef938c1
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4030
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
read_memory was doing autoexec-initialized commands, but wasn't using
ac_busy_delay to add delay or wait between the commands. This isn't the optimal
solution, but the whole read_memory sequence needs to be made more efficient
anyway, so this was the quick and dirty solution.
When ARM64 support was being merged, a comparison ended up being
inverted. This causes NULL pointer access when target attempts to
use core cache.
Change-Id: Ic8873ddd13dbdd8100856a71b4717f44cd336e23
Signed-off-by: Girts Folkmanis <opensource@girts.me>
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4042
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Replace the constants with the ones from the ISA spec, since those are
not updated as often.
Also delete a bunch of old code.
Change-Id: I9201b1455d64a9d2d203bb362fefaa68cbf35aeb
after handling of an exception in debug state, immediately
restore the original core state.
Change-Id: Ie53b63c9f19815f717f4df4390fbc13f0a204cc2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3996
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
to speed up debugging, don't load the complete register context
on a halt event, load only those registers that might be
clobbered during debugging.
Change-Id: I0b58e97aad6f28aefce4a52e870af61e1ef1a44f
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3995
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This patch contains a major overhaul of the target run control,
mainly for the sake of satisfying gdbs ideas of how a target
should respond to various control requests for the debugger.
The changes allow gdb a slightly better control on how cores
are stepped: a core can be single-stepped while
other cores remain halted or continue normal execution
until the single-stepped core halts again.
Also, on any halting event (user command or breakpoint) the
system is brought into a stable state with all cores halted
before the halt is signaled to the debugger.
This patch also transitions the target code to make use of the
new CTI abstraction instead of accessing CTI registers directly.
Change-Id: I8ddc9abb119e04580d671b57ee12240c3f5070a0
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3993
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
- rename "cortex_a" command group to "aarch64"
- remove default blank check, checksum and algorithm hooks
since they're not going to work in aarch64 mode anyway.
Change-Id: Ieb0046786ed9425baf6774c68f42a8285cc2aefd
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3991
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Make sure all core register caches are invalidated on reset
assert, make sure to re-init debug registers on deassert.
Change-Id: I82350d04cc3eaae5e35245d13d6c1fb0a8d59807
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3990
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
introduce armv8_set_dbgreg_bits() function to make register
bit-field modifications easier to read.
Change-Id: I6b06f66262587fd301d848c9e0645e8327653de7
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3989
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The aarch32 register cache is only a separate view of the aarch64
registers. Load aarch32 registers through their aarch64 equivalents.
Change-Id: I3e932dfb782f03d73d30d942b24db340a5749e47
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3988
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Mmu faults can not be prevented on aarch64, they need to be taken and
handled accordingly. Remove the remaining stub code.
Change-Id: I6241efa594fe6b963624f9628cdf1c8e46588223
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3987
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Not specific to ARMv8, the Cross Trigger Interface
deserves an independent access wrapper.
Change-Id: I84f8faad15ed3515e0fff7f6cc5d1109ef91a869
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3986
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reduce SLOCs in SCTLR retrieval and modification functions and make them
less complex.
Change-Id: Ida1a99c223743247f171b52eef80dc9886802101
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3982
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Use the correct opcode for Aarch32 state, both for the breakpoint
instruction itself and the cache handling functions.
Change-Id: I975fa67b1e577b54f5c672a01d516419c6a614b2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3981
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The remote bitbang implementation is really slow when reading back data.
During many operations, like writing a block of memory, we don't need to
see the return data. By communicating this to the lower layers, we get
huge speedups. Downloads to spike now are 295KB/s.
That means the gdbserver.py download test now runs to completion,
unfortunately it fails. Everything else is still passing, though, so I'm
committing this change.
Change-Id: I44cc9db1ade0908c1a12d09b23fc8e529a802d88
Not a great fix. There's still a problem with accessing 64-bit floating
point registers on 32-bit cores.
24 of the gdbserver.py tests pass now.
Change-Id: I69a88ef5fd5581e2c7bf1d78057fd474ae86ff93
Salvador Arroyo