Commit Graph

13 Commits

Author SHA1 Message Date
Tim Newsome efce094b40 Don't fake step for hwthread rtos. (#393)
Fake step is a hack introduced to make things work with real RTOSs that
have a concept of a current thread. The hwthread rtos always has access
to all threads, so doesn't need it.

This fixes a bug when running my MulticoreRegTest against HiFive
Unleashed where OpenOCD would return the registers of the wrong thread
after gdb stepped a hart.

Change-Id: I64f538a133fb078c05a0c6b8121388b0b9d7f1b8
2019-08-14 11:56:44 -07:00
Tim Newsome 79f9672615 Merge branch 'master' into from_upstream
Conflicts:
	src/flash/nor/at91sam4.c
	src/flash/nor/at91sam4l.c
	src/flash/nor/at91samd.c
	src/flash/nor/ath79.c
	src/flash/nor/atsame5.c
	src/flash/nor/cfi.c
	src/flash/nor/core.c
	src/flash/nor/fespi.c
	src/flash/nor/kinetis.c
	src/flash/nor/kinetis_ke.c
	src/flash/nor/lpc2000.c
	src/flash/nor/niietcm4.c
	src/flash/nor/nrf5.c
	src/flash/nor/numicro.c
	src/flash/nor/pic32mx.c
	src/flash/nor/stm32h7x.c
	src/flash/nor/stm32lx.c
	src/flash/nor/stmsmi.c
	src/flash/nor/tcl.c
	src/flash/nor/tms470.c
	src/flash/nor/virtual.c
	src/flash/nor/xmc4xxx.c
	src/rtos/hwthread.c
	src/rtos/rtos.c
	src/server/gdb_server.c
	src/target/riscv/riscv-011.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h

Change-Id: I9f0f373d45a9e5845bca83ca52e977f727ea4425
2019-04-03 12:38:27 -07:00
Matthias Welwarsky 85ba2dc4c6 rtos/hwthread: add hardware-thread pseudo rtos
This patch adds "hwthread", a pseudo rtos that represents cpu cores
in an SMP system as threads to gdb. This allows to debug SMP
system kernels in a more sensible manner and removes the current
atrocities of switching gdb manually between CPU cores to update
the context.

Change-Id: Ib781c6c34097689d21d9e02011e4d74a4a742379
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3999
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Graham Sanderson <graham.sanderson@gmail.com>
2019-03-08 12:54:47 +00:00
Tim Newsome 80ef54dba2 Rtos riscv (#350)
* Implement riscv_get_thread_reg().

This is necessary because riscv_get_gdb_reg_list() now reads all
registers, which ended up causing `-rtos riscv` to read all registers
whenever one was requested (because the register cache is wiped every
time we switch to a different hart).

CustomRegisterTest went from 1329s to 106s.

Change-Id: I8e9918b7a532d44bca927f67aae5ac34954a8d32

* Also implement riscv_set_reg().

Now all the `-rtos riscv` tests pass again, at regular speed.

Change-Id: I55164224672d9dcc9eb4d1184b47258ff3c2cff1

* Better error messages.

Change-Id: I4125f9a54750d9d0ee22c4fa84b9dd3f5af203f5

* Add target_get_gdb_reg_list_noread().

Being explicit about what's expected gets `-rtos riscv` back to `-rtos
hwthread` time.

Change-Id: I6e57390c2fe79b5e6799bfda980d89697e2e29f7

* Revert a change I made that has no effect.

I don't understand exactly what all this test protects against, and I
shouldn't change it unless I do.

Change-Id: Ib329d4e34d65d2b38559b89b7afb3678f439ad2c
2019-02-07 13:24:44 -08:00
Tim Newsome 220a97979f Use more compatible printf formatting.
Change-Id: I5d5b46f3e6c4f5abff1c0efa3ea8b4f589c1e635
2019-01-25 15:56:26 -08:00
Tim Newsome 96df1db7b1 Remove debug statements.
Change-Id: If37bc883fea0b83740bfd6a7fcb2091db0ac61f0
2019-01-25 14:48:22 -08:00
Tim Newsome afedcb337a WIP on hardware breakpoints.
This is messy, but contains at least some bugfixes.

39/43 tests pass now.

Change-Id: Ic9e8dad2a0ceb237e28c93906d1cd60876a5766d
2019-01-24 15:27:53 -08:00
Tim Newsome 348f15315e Don't reset current thread id on single step.
Now passing 36/45 tests.

Change-Id: I244b045f84397b058cf526e3bff238cb05d8ad06
2019-01-18 11:34:26 -08:00
Tim Newsome c1ef5f61c3 Fix reading of non-general registers for hwthread
Previously the code made the assumption (which is valid for conventional
RTOSs) that special registers (e.g. CSRs) are the same across threads.

26/45 tests pass.

Change-Id: Ibb3398790d7354a995d506772375d869f608f1f0
2019-01-17 15:01:47 -08:00
Tim Newsome c84d56debc rtos support to write registers on current thread
I don't understand how it was ever possible to change the registers on a
thread that's not the current active one when a halt happened. Really
instead of the RTOS tracking what the currently selected thread is, it
would make more sense to have gdb_server do that and simply pass it
along in every call to the RTOS layer.

Now MulticoreRegTest passes.

Change-Id: I399b9b2b05a147aa6b41463714ed3a39534b1fc8
2019-01-11 13:53:53 -08:00
Tim Newsome 4bb8bd005c Implement hwthread_get_thread_reg_list.
MulticoreRegTest now gets past the first check on all GPRs.

Change-Id: I35f3c51273542668985f7a86965c1e947fc12194
2019-01-07 08:48:49 -08:00
Tim Newsome 0736929512 Neuter hwthread_get_thread_reg_list so it builds
Change-Id: I07cf72ea1874ca7cb5557677ecb751c931174419
2019-01-03 12:47:14 -08:00
Matthias Welwarsky a01b079440 rtos/hwthread: add hardware-thread pseudo rtos
This patch adds "hwthread", a pseudo rtos that represents cpu cores
in an SMP system as threads to gdb. This allows to debug SMP
system kernels in a more sensible manner and removes the current
atrocities of switching gdb manually between CPU cores to update
the context.

Change-Id: Ib781c6c34097689d21d9e02011e4d74a4a742379
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>

Source: http://openocd.zylin.com/#/c/3999
2019-01-02 13:16:13 -08:00