if armv7a_l1_d_cache_clean_inval_all will fail, error value is never
forwarded. So make sure we do it from now.
Change-Id: I02acfaa938ec09f58df77191d13d8f4bb3308720
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4384
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Images build improperly (by simply concatenating separate images) were accepted,
but anything after the first end-of-file record *silently* ignored. Now emit warning
for intel and motorola images upon non-whitespace after first end-of-file record but
continue reading anyway.
ST ships some images broken that way in their CubeMX packages ...
Change-Id: I0c5d08fa90070fed11fb805c5f0dc39817048176
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4281
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
scan-build reported a couple of problems with code in aarch64.c,
this patch cleans them up. No functional changes.
Change-Id: Ie210237ddc840a8bbcd535f86a3a5faf473132f2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4346
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Some of these changes actually fix broken comparisons which could
occasionally fail. Others just clean up the code and make it more clear.
Change-Id: I6c398bdc45fa0d2716f48a74822457d1351f81a5
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4380
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Command
mdw 0 0x40000000
triggers Segmentation fault on an arm.
Size parameter is a nonsence that may happen e.g. if you
mistype mdw instead of mww.
Add checking for calloc() NULL return in mdb/h/w.
Use calloc() instead of malloc() as multiplication
count * sizeof(uint32_t) overflows for size >= 0x40000000.
Change-Id: I968c944d863d1173ef932a7077d526fccb9381ae
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4349
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Don't use atomic dap operations when not necessary. Also remove
loop trying to set core power request, didn't find a platform
where it actually worked and it's slowing examination down.
Change-Id: I44e5c2f289f951b8f4579f08a841172404a52053
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4143
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
added missing instructions from latest available ejtag specification
(MD00047 v6.1 at time of writting) for trace control, fast data channel
and pcsample.
Change-Id: I30293951611265ffc2bd896f9d3ca6b310e5cac6
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-on: http://openocd.zylin.com/3950
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This duration vs sample count is _significantly_ closer to the truth
than simply declaring the value to be 100Hz.
Change-Id: Ie8d8bdf1959e1aa7cead0631cd2c86afe77d1efc
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/4221
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Leverages the existing work that added profiling via DWT_PCSR.
hla_target doesn't have direct access to the mem_ap for doing a bulk
repeated read, but simply reading the DWT_PCSR register repeatedly is
still ~2 order of magnitude faster than halt/resume.
Change-Id: Ibe451aa95143694398370fdad6939cfb6191d56f
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/4220
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Use DWT_PCSR if present (reads nonzero); otherwise do halt-and-sample pc.
Signed-off-by: Simon Schubert <2@0x2c.org>
Change-Id: Id2dc4665e5008cc497a2e6e6493522d038d5af42
Reviewed-on: http://openocd.zylin.com/4211
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
We're using an I/O port reset by default. The only board currently
supported (Galileo) doesn't have SRST routed on the JTAG connector.
When using 'reset halt', we must rely on Reset Break because our
adapters don't have support for PREQ#/PRDY# signals.
Tested with Intel Galileo GEN2.
Change-Id: Ia406e31c156f8001717d5b6a08bd03f71de790d3
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Reviewed-on: http://openocd.zylin.com/4016
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
When testing with Intel Galileo GEN2 I have noticed a few iterations
where probemode entry took a little longer. At most I had to read
tapstatus twice. This patch uses a loop of up to 100 iterations to
wait for tapstatus to update with PM entry results.
Change-Id: I1c87d7dde715255b3fd2460d299b9493218533fc
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Reviewed-on: http://openocd.zylin.com/4013
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
These symbols are only used within this C source file. They don't need
to be exposed to the outside.
Change-Id: Idb04550ecca7f12c3fdc8c6447eeeb871961add3
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Reviewed-on: http://openocd.zylin.com/4012
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reported by thesourcerer on IRC.
Change-Id: I36d4d95de176a19fdd0bf80d8b419be6ca637e98
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3893
Tested-by: jenkins
Functions mem_ap_read() and mem_ap_write() incremented address even
if addrinc=false. I overlooked this fact and moved mem_ap_setup_tar()
set wrong addresses in no-incr mode.
Fixed by preventing address increment in no-incr mode.
Change-Id: I512e12a6a64e30cf6bc5bf77e3d57d35cc33e058
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Suggested-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/4326
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
MEM-AP access through banked data registers MEM_AP_REG_BD0..3
does not increment TAR regardless of the current autoincrement mode.
mem_ap_read_u32() and mem_ap_write_u32() can keep the current
autoincrement mode instead of switching autoincrement off.
Change-Id: Ib7ec688d3e04f1da678363cd2819ce90e8910e58
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4163
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Problem: If the same memory location is accessed alternatively
by MEM-AP banked data registers without autoincrement and by standard
autoincremented read/write, TAR register is not updated correctly.
How to replicate: On a Cortex-M issue
mdw 0xe000edf0
multiple times. When poll is on (poll reads the same memory location)
only the first read is correct.
0xe000edf0: 01000000
0xe000edf0: 00000000
0xe000edf0: 20002640
0xe000edf0: 01000000
0xe000edf0: 00000000
0xe000edf0: 00000000
No problems with poll off.
0xe000edf0: 01000000
0xe000edf0: 01000000
0xe000edf0: 01000000
mem_ap_setup_tar() writes to MEM_AP_REG_TAR if requested TAR value
changed or CSW_ADDRINC_... is currently active.
However if an autoincremented access has been issued and autoinc
switched off in CSW afterwards, TAR does not get updated.
The change introduces mem_ap_update_tar_cache() which is called
after queuing of any access to MEM_AP_REG_DRW. It simulates
TAR increment to keep tar_value in sync with MEM_AP.
Crossing tar autoincrement block boundary invalidates cached value.
mem_ap_write() and mem_ap_read() do not check tar autoincrement
block boundary, mem_ap_setup_tar() is called before each transfer instead.
dap_invalidate_cache() is introduced to ensure invalidation
of all cached values during dap_dp_init() and swd_connect()
Change-Id: I815c2283d2989cffd6ea9a4100ce2f29dc3fb7b4
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4162
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The existing code only used Memory Access mode to read memory,
which uses 32 bit operations only.
Rework the code to check the alignment/size of the read/write operation,
and use the Memory Access mode to read aligned 32 bit memory.
When using unaligned access, or 8 or 16 bit reads, use LDR{BHW} and STR{BHW}
instead.
The exception handling is still the same as it was before (meaning it breaks
when things go wrong), but I can now read an 8 bit register correctly.
Change-Id: I739a5ee825c0226ed4a89c32895cc2a047b8dc15
Signed-off-by: Bas Vermeulen <bas@daedalean.ai>
Reviewed-on: http://openocd.zylin.com/4301
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Events reset-halt-pre, reset-halt-post, reset-wait-pre and
reset-wait-post are not used anywhere.
Change-Id: I9a0f94875b102d9b08f6c2fd9d73a9f05f8e8e79
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4285
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
New STM8 target based mostly on mips4k. Target communication
through STLINK/SWIM. No flash driver yet but it is still possible
to program flash through load_image command. The usual target debug
methods are implemented.
Change-Id: I7216f231d3ac7c70cae20f1cd8463c2ed864a329
Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com>
Reviewed-on: http://openocd.zylin.com/3953
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The dhcsr_save variable was used to save the value of
cortex_m->dcb_dhcsr so it could be restored later. However, all writes
in between the save and the restore use mem_ap_write_atomic_u32, not
cortex_m_write_debug_halt_mask, which means cortex_m->dcb_dhcsr isn’t
changed anyway. Delete the unnecessary local.
Change-Id: I064a3134e21398e1ecfc9f1fa7efd7b020b52341
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4240
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
In cortex_m_assert_reset, in two locations, DHCSR is written directly
using mem_ap_write_u32. This means that the cached version,
target_to_cm(target)->dcb_dhcsr, is not updated when these writes are
performed, so subsequent writes to DHCSR that use
cortex_m_write_debug_halt_mask will change those bits back to their old
values which, unless modified in that particular invocation, come from
the cache. This causes an actual, observable bug on an STM32F7 in which
running “reset run” immediately after “program” can in some cases result
in execution proceeding with C_MASKINTS set (it is cleared on line 1021
but is then set immediately afterward in cortex_m_clear_halt), causing
failure of the application. Replace these mem_ap_write_u32 calls with
cortex_m_write_debug_halt_mask calls to do the same jobs.
Change-Id: Id35ca7f6057c2df2ba9cd67c53a73b50816d0b71
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4239
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
GCC7 with -Wall warns about possible string truncation with
snprint()-type functions with "directive output may be truncated writing
1 byte into a region of size between 0 and 9
[-Werror=format-truncation=]" + "note: ‘snprintf’ output between 5 and
14 bytes into a destination of size 12" (or similar). Fix this by
increasing sizes of buffers.
See https://gcc.gnu.org/gcc-7/changes.html
Change-Id: Ib848f2a56dd658783534158947ae1be7c0e99d45
Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-on: http://openocd.zylin.com/4175
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
GCC7 with -Wextra warns about switch-case blocks which fallthrough with
"this statement may fall through [-Werror=implicit-fallthrough=]". This
can be fixed by adding "special" comments: "/* fallthrough */".
See https://gcc.gnu.org/gcc-7/changes.html
Change-Id: Iba0be791dbdd86984489b2d9a0592bb59828da1e
Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-on: http://openocd.zylin.com/4174
Tested-by: jenkins
Commit 47b8cf842 changed the fixed type of the value argument to snprint
but didn't change the format string to match for sizes != 64 bit.
Change-Id: I908b06f49ab69d04224282949190a0de883048e0
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/4167
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Philipp Guehring <pg@futureware.at>
Supported SoCs: AR71xx, AR724x, AR91xx, AR93xx, QCA9558
Extended and revised version of my original patch submitted by Dmytro
here: http://openocd.zylin.com/#/c/3390
This driver is using pure SPI mode, so the flash base address is not
used except some flash commands (e.g. "flash program") need it to
distinguish the banks.
Example config with all 3 chip selects:
flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
Example usage:
> flash probe flash0
Found flash device 'win w25q128fv' (ID 0x001840ef)
flash 'ath79' found at 0x00000000
> flash probe flash1
No SPI flash found
> flash probe flash2
No SPI flash found
> flash banks
> flash read_bank flash0 /tmp/test.bin 0x00000000 0x1000
reading 4096 bytes from flash @0x00000000
wrote 4096 bytes to file /tmp/test.bin from flash bank 0 at offset
0x00000000 in 28.688066s (0.139 KiB/s)
Change-Id: I5feb697722c07e83a9c1b361a9db7b06bc699aa8
Signed-off-by: Tobias Diedrich <ranma+openocd@tdiedrich.de>
Reviewed-on: http://openocd.zylin.com/3612
Tested-by: jenkins
Reviewed-by: Dmytro <dioptimizer@hotmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
There is no need to implement scan code in functions
mips_ejtag_get_idcode/impcode(), use mips_ejtag_drscan_32().
Impcode/idcode saved in ejtag.info.
Reorder the code in the callers of this functions.
Change-Id: Ia829c783a0b24c6a65cade736113fa6f67b0a170
Signed-off-by: Salvador Arroyo <salvador@telecable.es>
Reviewed-on: http://openocd.zylin.com/4003
Tested-by: jenkins
Reviewed-by: Peter Mamonov <pmamonov@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Breakpoint setting based on length (kind) only.
Added 16bit aligned 32bit software breakpoints
support and same filtering before setting
breakpoint.
Set the required isa bit in hardware breakpoints.
Drop the isa bit in software breakpoints.
Change-Id: I7020f27be16015194b76f385d9b8e5af496d0dfc
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4124
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Read and save configuration registers, up to 4.
Config3 holds the micromips implementation info.
Added isa implementation info to mips32_common.
Added isa filter to avoid common mistakes, but only
if one isa mode is implemented.
When resuming the isa requested is set if more than
one isa mode is implemented.
Change-Id: I1d6526c5525bffac8d75e031b842b2edc6310e28
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4123
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
