The openocd-0.12.0-rc2 release candidate

Signed-off-by: Paul Fertser <fercerpav@gmail.com>

NEWS

@@ -121,7 +121,7 @@ This release also contains a number of other important functional and
 cosmetic bugfixes. For more details about what has changed since the
 last release, see the git repository history:
 
-http://sourceforge.net/p/openocd/code/ci/v0.12.0-rc1/log/?path=
+http://sourceforge.net/p/openocd/code/ci/v0.12.0-rc2/log/?path=
 
 
 For older NEWS, see the NEWS files associated with each release

README

@@ -219,7 +219,10 @@ You'll also need:
 
 - make
 - libtool
-- pkg-config >= 0.23 (or compatible)
+- pkg-config >= 0.23 or pkgconf
+
+OpenOCD uses jimtcl library; build from git can retrieve jimtcl as git
+submodule.
 
 Additionally, for building from git:
 
@@ -227,14 +230,26 @@ Additionally, for building from git:
 - automake >= 1.14
 - texinfo >= 5.0
 
-USB-based adapters depend on libusb-1.0. A compatible implementation, such as
-FreeBSD's, additionally needs the corresponding .pc files.
+Optional USB-based adapter drivers need libusb-1.0.
 
-USB-Blaster, ASIX Presto and OpenJTAG interface adapter
+Optional USB-Blaster, ASIX Presto and OpenJTAG interface adapter
 drivers need:
   - libftdi: http://www.intra2net.com/en/developer/libftdi/index.php
 
-CMSIS-DAP support needs HIDAPI library.
+Optional CMSIS-DAP adapter driver needs HIDAPI library.
+
+Optional linuxgpiod adapter driver needs libgpiod library.
+
+Optional JLink adapter driver needs libjaylink; build from git can
+retrieve libjaylink as git submodule.
+
+Optional ARM disassembly needs capstone library.
+
+Optional development script checkpatch needs:
+
+- perl
+- python
+- python-ply
 
 Permissions delegation
 ----------------------

configure.ac

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 AC_PREREQ([2.69])
-AC_INIT([openocd], [0.12.0-rc1],
+AC_INIT([openocd], [0.12.0-rc2],
   [OpenOCD Mailing List <openocd-devel@lists.sourceforge.net>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 AC_CONFIG_AUX_DIR([build-aux])
@@ -631,7 +631,6 @@ AS_IF([test "x$enable_capstone" != xno], [
 	PKG_CHECK_MODULES([CAPSTONE], [capstone], [
 		AC_DEFINE([HAVE_CAPSTONE], [1], [1 if you have Capstone disassembly framework.])
 	], [
-		AC_DEFINE([HAVE_CAPSTONE], [0], [0 if you don't have Capstone disassembly framework.])
 		if test "x$enable_capstone" != xauto; then
 			AC_MSG_ERROR([--with-capstone was given, but test for Capstone failed])
 		fi
@@ -639,6 +638,10 @@ AS_IF([test "x$enable_capstone" != xno], [
 	])
 ])
 
+AS_IF([test "x$enable_capstone" == xno], [
+	AC_DEFINE([HAVE_CAPSTONE], [0], [0 if you don't have Capstone disassembly framework.])
+])
+
 for hidapi_lib in hidapi hidapi-hidraw hidapi-libusb; do
 	PKG_CHECK_MODULES([HIDAPI],[$hidapi_lib],[
 		use_hidapi=yes

doc/openocd.texi

@@ -19,7 +19,7 @@ dated @value{UPDATED},
 of the Open On-Chip Debugger (OpenOCD).
 
 @itemize @bullet
-@item Copyright @copyright{} 2008 The OpenOCD Project
+@item Copyright @copyright{} 2008-2022 The OpenOCD Project
 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
@@ -1785,7 +1785,6 @@ $_TARGETNAME configure -work-area-phys 0x00200000 \
              -work-area-size 0x4000 -work-area-backup 0
 @end example
 
-@anchor{definecputargetsworkinginsmp}
 @subsection Define CPU targets working in SMP
 @cindex SMP
 After setting targets, you can define a list of targets working in SMP.
@@ -1939,7 +1938,6 @@ For an example of this scheme see LPC2000 target config files.
 The @code{init_boards} procedure is a similar concept concerning board config files
 (@xref{theinitboardprocedure,,The init_board procedure}.)
 
-@anchor{theinittargeteventsprocedure}
 @subsection The init_target_events procedure
 @cindex init_target_events procedure
 
@@ -2468,7 +2466,6 @@ the generic mapping may not support all of the listed options.
 Returns the name of the debug adapter driver being used.
 @end deffn
 
-@anchor{adapter_usb_location}
 @deffn {Config Command} {adapter usb location} [<bus>-<port>[.<port>]...]
 Displays or specifies the physical USB port of the adapter to use. The path
 roots at @var{bus} and walks down the physical ports, with each
@@ -3504,11 +3501,11 @@ Espressif JTAG driver to communicate with ESP32-C3, ESP32-S3 chips and ESP USB B
 These chips have built-in JTAG circuitry and can be debugged without any additional hardware.
 Only an USB cable connected to the D+/D- pins is necessary.
 
-@deffn {Config Command} {espusbjtag tdo}
+@deffn {Command} {espusbjtag tdo}
 Returns the current state of the TDO line
 @end deffn
 
-@deffn {Config Command} {espusbjtag setio} setio
+@deffn {Command} {espusbjtag setio} setio
 Manually set the status of the output lines with the order of (tdi tms tck trst srst)
 @example
 espusbjtag setio 0 1 0 1 0
@@ -6205,7 +6202,6 @@ the flash.
 @end deffn
 @end deffn
 
-@anchor{at91samd}
 @deffn {Flash Driver} {at91samd}
 @cindex at91samd
 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
@@ -9502,14 +9498,14 @@ requests by using a special SVC instruction that is trapped at the
 Supervisor Call vector by OpenOCD.
 @end deffn
 
-@deffn {Command} {arm semihosting_redirect} (@option{disable} | @option{tcp} <port>
-[@option{debug}|@option{stdio}|@option{all})
+@deffn {Command} {arm semihosting_redirect} (@option{disable} | @option{tcp} <port> [@option{debug}|@option{stdio}|@option{all}])
 @cindex ARM semihosting
 Redirect semihosting messages to a specified TCP port.
 
 This command redirects debug (READC, WRITEC and WRITE0) and stdio (READ, WRITE)
 semihosting operations to the specified TCP port.
 The command allows to select which type of operations to redirect (debug, stdio, all (default)).
+
 Note: for stdio operations, only I/O from/to ':tt' file descriptors are redirected.
 @end deffn
 
@@ -10653,6 +10649,16 @@ $_TARGETNAME expose_custom 32=myregister
 @end example
 @end deffn
 
+@deffn {Command} {riscv info}
+Displays some information OpenOCD detected about the target.
+@end deffn
+
+@deffn {Command} {riscv reset_delays} [wait]
+OpenOCD learns how many Run-Test/Idle cycles are required between scans to avoid
+encountering the target being busy. This command resets those learned values
+after `wait` scans. It's only useful for testing OpenOCD itself.
+@end deffn
+
 @deffn {Command} {riscv set_command_timeout_sec} [seconds]
 Set the wall-clock timeout (in seconds) for individual commands. The default
 should work fine for all but the slowest targets (eg. simulators).
@@ -10663,12 +10669,7 @@ Set the maximum time to wait for a hart to come out of reset after reset is
 deasserted.
 @end deffn
 
-@deffn {Command} {riscv set_scratch_ram} none|[address]
-Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'.
-This is used to access 64-bit floating point registers on 32-bit targets.
-@end deffn
-
-@deffn Command {riscv set_mem_access} method1 [method2] [method3]
+@deffn {Command} {riscv set_mem_access} method1 [method2] [method3]
 Specify which RISC-V memory access method(s) shall be used, and in which order
 of priority. At least one method must be specified.
 
@@ -10976,12 +10977,12 @@ NXP}.
 
 @subsection Xtensa Configuration Commands
 
-@deffn {Command} {xtensa xtdef} (@option{LX}|@option{NX})
+@deffn {Config Command} {xtensa xtdef} (@option{LX}|@option{NX})
 Configure the Xtensa target architecture. Currently, Xtensa support is limited
 to LX6, LX7, and NX cores.
 @end deffn
 
-@deffn {Command} {xtensa xtopt} option value
+@deffn {Config Command} {xtensa xtopt} option value
 Configure Xtensa target options that are relevant to the debug subsystem.
 @var{option} is one of: @option{arnum}, @option{windowed},
 @option{cpenable}, @option{exceptions}, @option{intnum}, @option{hipriints},
@@ -10993,35 +10994,35 @@ NOTE: Some options are specific to Xtensa LX or Xtensa NX architecture, while
 others may be common to both but have different valid ranges.
 @end deffn
 
-@deffn {Command} {xtensa xtmem} (@option{iram}|@option{dram}|@option{sram}|@option{irom}|@option{drom}|@option{srom}) baseaddr bytes
+@deffn {Config Command} {xtensa xtmem} (@option{iram}|@option{dram}|@option{sram}|@option{irom}|@option{drom}|@option{srom}) baseaddr bytes
 Configure Xtensa target memory. Memory type determines access rights,
 where RAMs are read/write while ROMs are read-only. @var{baseaddr} and
 @var{bytes} are both integers, typically hexadecimal and decimal, respectively.
 @end deffn
 
-@deffn {Command} {xtensa xtmem} (@option{icache}|@option{dcache}) linebytes cachebytes ways [writeback]
+@deffn {Config Command} {xtensa xtmem} (@option{icache}|@option{dcache}) linebytes cachebytes ways [writeback]
 Configure Xtensa processor cache. All parameters are required except for
 the optional @option{writeback} parameter; all are integers.
 @end deffn
 
-@deffn {Command} {xtensa xtmpu} numfgseg minsegsz lockable execonly
+@deffn {Config Command} {xtensa xtmpu} numfgseg minsegsz lockable execonly
 Configure an Xtensa Memory Protection Unit (MPU). MPUs can restrict access
 and/or control cacheability of specific address ranges, but are lighter-weight
 than a full traditional MMU. All parameters are required; all are integers.
 @end deffn
 
-@deffn {Command} {xtensa xtmmu} numirefillentries numdrefillentries
+@deffn {Config Command} {xtensa xtmmu} numirefillentries numdrefillentries
 (Xtensa-LX only) Configure an Xtensa Memory Management Unit (MMU). Both
 parameters are required; both are integers.
 @end deffn
 
-@deffn {Command} {xtensa xtregs} numregs
+@deffn {Config Command} {xtensa xtregs} numregs
 Configure the total number of registers for the Xtensa core. Configuration
 logic expects to subsequently process this number of @code{xtensa xtreg}
 definitions. @var{numregs} is an integer.
 @end deffn
 
-@deffn {Command} {xtensa xtregfmt} (@option{sparse}|@option{contiguous}) [general]
+@deffn {Config Command} {xtensa xtregfmt} (@option{sparse}|@option{contiguous}) [general]
 Configure the type of register map used by GDB to access the Xtensa core.
 Generic Xtensa tools (e.g. xt-gdb) require @option{sparse} mapping (default) while
 Espressif tools expect @option{contiguous} mapping. Contiguous mapping takes an
@@ -11029,7 +11030,7 @@ additional, optional integer parameter @option{numgregs}, which specifies the nu
 of general registers used in handling g/G packets.
 @end deffn
 
-@deffn {Command} {xtensa xtreg} name offset
+@deffn {Config Command} {xtensa xtreg} name offset
 Configure an Xtensa core register. All core registers are 32 bits wide,
 while TIE and user registers may have variable widths. @var{name} is a
 character string identifier while @var{offset} is a hexadecimal integer.

src/flash/nor/at91samd.c

@@ -543,7 +543,8 @@ static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
 	}
 
 	/* Issue the NVM command */
-	res = target_write_u16(target,
+	/* 32-bit write is used to ensure atomic operation on ST-Link */
+	res = target_write_u32(target,
 			SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
 	if (res != ERROR_OK)
 		return res;

src/flash/nor/rp2040.c

@@ -87,7 +87,7 @@ static uint32_t rp2040_lookup_symbol(struct target *target, uint32_t tag, uint16
 }
 
 static int rp2040_call_rom_func(struct target *target, struct rp2040_flash_bank *priv,
-		uint16_t func_offset, uint32_t argdata[], unsigned int n_args)
+		uint16_t func_offset, uint32_t argdata[], unsigned int n_args, int timeout_ms)
 {
 	char *regnames[4] = { "r0", "r1", "r2", "r3" };
 
@@ -99,8 +99,7 @@ static int rp2040_call_rom_func(struct target *target, struct rp2040_flash_bank
 	}
 	target_addr_t stacktop = priv->stack->address + priv->stack->size;
 
-	LOG_DEBUG("Calling ROM func @0x%" PRIx16 " with %d arguments", func_offset, n_args);
-	LOG_DEBUG("Calling on core \"%s\"", target->cmd_name);
+	LOG_TARGET_DEBUG(target, "Calling ROM func @0x%" PRIx16 " with %u arguments", func_offset, n_args);
 
 	struct reg_param args[ARRAY_SIZE(regnames) + 2];
 	struct armv7m_algorithm alg_info;
@@ -112,11 +111,12 @@ static int rp2040_call_rom_func(struct target *target, struct rp2040_flash_bank
 	/* Pass function pointer in r7 */
 	init_reg_param(&args[n_args], "r7", 32, PARAM_OUT);
 	buf_set_u32(args[n_args].value, 0, 32, func_offset);
+	/* Setup stack */
 	init_reg_param(&args[n_args + 1], "sp", 32, PARAM_OUT);
 	buf_set_u32(args[n_args + 1].value, 0, 32, stacktop);
+	unsigned int n_reg_params = n_args + 2;	/* User arguments + r7 + sp */
 
-
-	for (unsigned int i = 0; i < n_args + 2; ++i)
+	for (unsigned int i = 0; i < n_reg_params; ++i)
 		LOG_DEBUG("Set %s = 0x%" PRIx32, args[i].reg_name, buf_get_u32(args[i].value, 0, 32));
 
 	/* Actually call the function */
@@ -125,42 +125,82 @@ static int rp2040_call_rom_func(struct target *target, struct rp2040_flash_bank
 	int err = target_run_algorithm(
 		target,
 		0, NULL,          /* No memory arguments */
-		n_args + 1, args, /* User arguments + r7 */
+		n_reg_params, args, /* User arguments + r7 + sp */
 		priv->jump_debug_trampoline, priv->jump_debug_trampoline_end,
-		3000, /* 3s timeout */
+		timeout_ms,
 		&alg_info
 	);
-	for (unsigned int i = 0; i < n_args + 2; ++i)
-		destroy_reg_param(&args[i]);
-	if (err != ERROR_OK)
-		LOG_ERROR("Failed to invoke ROM function @0x%" PRIx16 "\n", func_offset);
-	return err;
 
+	for (unsigned int i = 0; i < n_reg_params; ++i)
+		destroy_reg_param(&args[i]);
+
+	if (err != ERROR_OK)
+		LOG_ERROR("Failed to invoke ROM function @0x%" PRIx16, func_offset);
+
+	return err;
 }
 
-static int stack_grab_and_prep(struct flash_bank *bank)
+/* Finalize flash write/erase/read ID
+ * - flush cache
+ * - enters memory-mapped (XIP) mode to make flash data visible
+ * - deallocates target ROM func stack if previously allocated
+ */
+static int rp2040_finalize_stack_free(struct flash_bank *bank)
 {
 	struct rp2040_flash_bank *priv = bank->driver_priv;
+	struct target *target = bank->target;
+
+	/* Always flush before returning to execute-in-place, to invalidate stale
+	 * cache contents. The flush call also restores regular hardware-controlled
+	 * chip select following a rp2040_flash_exit_xip().
+	 */
+	LOG_DEBUG("Flushing flash cache after write behind");
+	int err = rp2040_call_rom_func(target, priv, priv->jump_flush_cache, NULL, 0, 1000);
+	if (err != ERROR_OK) {
+		LOG_ERROR("Failed to flush flash cache");
+		/* Intentionally continue after error and try to setup xip anyway */
+	}
+
+	LOG_DEBUG("Configuring SSI for execute-in-place");
+	err = rp2040_call_rom_func(target, priv, priv->jump_enter_cmd_xip, NULL, 0, 1000);
+	if (err != ERROR_OK)
+		LOG_ERROR("Failed to set SSI to XIP mode");
+
+	target_free_working_area(target, priv->stack);
+	priv->stack = NULL;
+	return err;
+}
+
+/* Prepare flash write/erase/read ID
+ * - allocates a stack for target ROM func
+ * - switches the SPI interface from memory-mapped mode to direct command mode
+ * Always pair with a call of rp2040_finalize_stack_free()
+ * after flash operation finishes or fails.
+ */
+static int rp2040_stack_grab_and_prep(struct flash_bank *bank)
+{
+	struct rp2040_flash_bank *priv = bank->driver_priv;
+	struct target *target = bank->target;
 
 	/* target_alloc_working_area always allocates multiples of 4 bytes, so no worry about alignment */
 	const int STACK_SIZE = 256;
-	int err = target_alloc_working_area(bank->target, STACK_SIZE, &priv->stack);
+	int err = target_alloc_working_area(target, STACK_SIZE, &priv->stack);
 	if (err != ERROR_OK) {
 		LOG_ERROR("Could not allocate stack for flash programming code");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
 	LOG_DEBUG("Connecting internal flash");
-	err = rp2040_call_rom_func(bank->target, priv, priv->jump_connect_internal_flash, NULL, 0);
+	err = rp2040_call_rom_func(target, priv, priv->jump_connect_internal_flash, NULL, 0, 1000);
 	if (err != ERROR_OK) {
-		LOG_ERROR("RP2040 erase: failed to connect internal flash");
+		LOG_ERROR("Failed to connect internal flash");
 		return err;
 	}
 
 	LOG_DEBUG("Kicking flash out of XIP mode");
-	err = rp2040_call_rom_func(bank->target, priv, priv->jump_flash_exit_xip, NULL, 0);
+	err = rp2040_call_rom_func(target, priv, priv->jump_flash_exit_xip, NULL, 0, 1000);
 	if (err != ERROR_OK) {
-		LOG_ERROR("RP2040 erase: failed to exit flash XIP mode");
+		LOG_ERROR("Failed to exit flash XIP mode");
 		return err;
 	}
 
@@ -173,16 +213,27 @@ static int rp2040_flash_write(struct flash_bank *bank, const uint8_t *buffer, ui
 
 	struct rp2040_flash_bank *priv = bank->driver_priv;
 	struct target *target = bank->target;
-	struct working_area *bounce;
 
-	int err = stack_grab_and_prep(bank);
+	if (target->state != TARGET_HALTED) {
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	struct working_area *bounce = NULL;
+
+	int err = rp2040_stack_grab_and_prep(bank);
 	if (err != ERROR_OK)
-		return err;
+		goto cleanup;
 
-	const unsigned int chunk_size = target_get_working_area_avail(target);
-	if (target_alloc_working_area(target, chunk_size, &bounce) != ERROR_OK) {
+	unsigned int avail_pages = target_get_working_area_avail(target) / priv->dev->pagesize;
+	/* We try to allocate working area rounded down to device page size,
+	 * al least 1 page, at most the write data size
+	 */
+	unsigned int chunk_size = MIN(MAX(avail_pages, 1) * priv->dev->pagesize, count);
+	err = target_alloc_working_area(target, chunk_size, &bounce);
+	if (err != ERROR_OK) {
 		LOG_ERROR("Could not allocate bounce buffer for flash programming. Can't continue");
-		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+		goto cleanup;
 	}
 
 	LOG_DEBUG("Allocated flash bounce buffer @" TARGET_ADDR_FMT, bounce->address);
@@ -200,7 +251,8 @@ static int rp2040_flash_write(struct flash_bank *bank, const uint8_t *buffer, ui
 			bounce->address, /* data */
 			write_size /* count */
 		};
-		err = rp2040_call_rom_func(target, priv, priv->jump_flash_range_program, args, ARRAY_SIZE(args));
+		err = rp2040_call_rom_func(target, priv, priv->jump_flash_range_program,
+								 args, ARRAY_SIZE(args), 3000);
 		if (err != ERROR_OK) {
 			LOG_ERROR("Failed to invoke flash programming code on target");
 			break;
@@ -210,36 +262,32 @@ static int rp2040_flash_write(struct flash_bank *bank, const uint8_t *buffer, ui
 		offset += write_size;
 		count -= write_size;
 	}
+
+cleanup:
 	target_free_working_area(target, bounce);
 
-	if (err != ERROR_OK)
-		return err;
+	rp2040_finalize_stack_free(bank);
 
-	/* Flash is successfully programmed. We can now do a bit of poking to make the flash
-	   contents visible to us via memory-mapped (XIP) interface in the 0x1... memory region */
-	LOG_DEBUG("Flushing flash cache after write behind");
-	err = rp2040_call_rom_func(bank->target, priv, priv->jump_flush_cache, NULL, 0);
-	if (err != ERROR_OK) {
-		LOG_ERROR("RP2040 write: failed to flush flash cache");
-		return err;
-	}
-	LOG_DEBUG("Configuring SSI for execute-in-place");
-	err = rp2040_call_rom_func(bank->target, priv, priv->jump_enter_cmd_xip, NULL, 0);
-	if (err != ERROR_OK)
-		LOG_ERROR("RP2040 write: failed to flush flash cache");
 	return err;
 }
 
 static int rp2040_flash_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
 {
 	struct rp2040_flash_bank *priv = bank->driver_priv;
+	struct target *target = bank->target;
+
+	if (target->state != TARGET_HALTED) {
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
 	uint32_t start_addr = bank->sectors[first].offset;
 	uint32_t length = bank->sectors[last].offset + bank->sectors[last].size - start_addr;
 	LOG_DEBUG("RP2040 erase %d bytes starting at 0x%" PRIx32, length, start_addr);
 
-	int err = stack_grab_and_prep(bank);
+	int err = rp2040_stack_grab_and_prep(bank);
 	if (err != ERROR_OK)
-		return err;
+		goto cleanup;
 
 	LOG_DEBUG("Remote call flash_range_erase");
 
@@ -257,10 +305,15 @@ static int rp2040_flash_erase(struct flash_bank *bank, unsigned int first, unsig
 	https://github.com/raspberrypi/pico-bootrom/blob/master/bootrom/program_flash_generic.c
 
 	In theory, the function algorithm provides for erasing both a smaller "sector" (4096 bytes) and
-	an optional larger "block" (size and command provided in args).  OpenOCD's spi.c only uses "block" sizes.
+	an optional larger "block" (size and command provided in args).
 	*/
 
-	err = rp2040_call_rom_func(bank->target, priv, priv->jump_flash_range_erase, args, ARRAY_SIZE(args));
+	int timeout_ms = 2000 * (last - first) + 1000;
+	err = rp2040_call_rom_func(target, priv, priv->jump_flash_range_erase,
+							args, ARRAY_SIZE(args), timeout_ms);
+
+cleanup:
+	rp2040_finalize_stack_free(bank);
 
 	return err;
 }
@@ -289,11 +342,46 @@ static int rp2040_ssel_active(struct target *target, bool active)
 	return ERROR_OK;
 }
 
+static int rp2040_spi_read_flash_id(struct target *target, uint32_t *devid)
+{
+	uint32_t device_id = 0;
+	const target_addr_t ssi_dr0 = 0x18000060;
+
+	int err = rp2040_ssel_active(target, true);
+
+	/* write RDID request into SPI peripheral's FIFO */
+	for (int count = 0; (count < 4) && (err == ERROR_OK); count++)
+		err = target_write_u32(target, ssi_dr0, SPIFLASH_READ_ID);
+
+	/* by this time, there is a receive FIFO entry for every write */
+	for (int count = 0; (count < 4) && (err == ERROR_OK); count++) {
+		uint32_t status;
+		err = target_read_u32(target, ssi_dr0, &status);
+
+		device_id >>= 8;
+		device_id |= (status & 0xFF) << 24;
+	}
+
+	if (err == ERROR_OK)
+		*devid = device_id >> 8;
+
+	int err2 = rp2040_ssel_active(target, false);
+	if (err2 != ERROR_OK)
+		LOG_ERROR("SSEL inactive failed");
+
+	return err;
+}
+
 static int rp2040_flash_probe(struct flash_bank *bank)
 {
 	struct rp2040_flash_bank *priv = bank->driver_priv;
 	struct target *target = bank->target;
 
+	if (target->state != TARGET_HALTED) {
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
 	int err = rp2040_lookup_symbol(target, FUNC_DEBUG_TRAMPOLINE, &priv->jump_debug_trampoline);
 	if (err != ERROR_OK) {
 		LOG_ERROR("Debug trampoline not found in RP2040 ROM.");
@@ -344,34 +432,16 @@ static int rp2040_flash_probe(struct flash_bank *bank)
 		return err;
 	}
 
-	err = stack_grab_and_prep(bank);
-	if (err != ERROR_OK)
-		return err;
+	err = rp2040_stack_grab_and_prep(bank);
 
 	uint32_t device_id = 0;
-	const target_addr_t ssi_dr0 = 0x18000060;
+	if (err == ERROR_OK)
+		err = rp2040_spi_read_flash_id(target, &device_id);
 
-	err = rp2040_ssel_active(target, true);
+	rp2040_finalize_stack_free(bank);
 
-	/* write RDID request into SPI peripheral's FIFO */
-	for (int count = 0; (count < 4) && (err == ERROR_OK); count++)
-		err = target_write_u32(target, ssi_dr0, SPIFLASH_READ_ID);
-
-	/* by this time, there is a receive FIFO entry for every write */
-	for (int count = 0; (count < 4) && (err == ERROR_OK); count++) {
-		uint32_t status;
-		err = target_read_u32(target, ssi_dr0, &status);
-
-		device_id >>= 8;
-		device_id |= (status & 0xFF) << 24;
-	}
-	device_id >>= 8;
-
-	err = rp2040_ssel_active(target, false);
-	if (err != ERROR_OK) {
-		LOG_ERROR("SSEL inactive failed");
+	if (err != ERROR_OK)
 		return err;
-	}
 
 	/* search for a SPI flash Device ID match */
 	priv->dev = NULL;

src/jtag/adapter.h

@@ -117,7 +117,7 @@ const char *adapter_get_required_serial(void);
 const char *adapter_gpio_get_name(enum adapter_gpio_config_index idx);
 
 /**
- * Retrieves gpio configuration set with command 'adapter gpio <signal_name>'
+ * Retrieves gpio configuration set with command "adapter gpio <signal_name>"
  */
 const struct adapter_gpio_config *adapter_gpio_get_config(void);
 

src/jtag/drivers/bcm2835gpio.c

@@ -57,6 +57,15 @@ static struct initial_gpio_state {
 } initial_gpio_state[ADAPTER_GPIO_IDX_NUM];
 static uint32_t initial_drive_strength_etc;
 
+static inline void bcm2835_gpio_synchronize(void)
+{
+	/* Ensure that previous writes to GPIO registers are flushed out of
+	 * the inner shareable domain to prevent pipelined writes to the
+	 * same address being merged.
+	 */
+	__sync_synchronize();
+}
+
 static bool is_gpio_config_valid(enum adapter_gpio_config_index idx)
 {
 	/* Only chip 0 is supported, accept unset value (-1) too */
@@ -96,6 +105,7 @@ static void set_gpio_value(const struct adapter_gpio_config *gpio_config, int va
 		}
 		break;
 	}
+	bcm2835_gpio_synchronize();
 }
 
 static void restore_gpio(enum adapter_gpio_config_index idx)
@@ -109,6 +119,7 @@ static void restore_gpio(enum adapter_gpio_config_index idx)
 				GPIO_CLR = 1 << adapter_gpio_config[idx].gpio_num;
 		}
 	}
+	bcm2835_gpio_synchronize();
 }
 
 static void initialize_gpio(enum adapter_gpio_config_index idx)
@@ -143,6 +154,7 @@ static void initialize_gpio(enum adapter_gpio_config_index idx)
 	/* Direction for non push-pull is already set by set_gpio_value() */
 	if (adapter_gpio_config[idx].drive == ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL)
 		OUT_GPIO(adapter_gpio_config[idx].gpio_num);
+	bcm2835_gpio_synchronize();
 }
 
 static bb_value_t bcm2835gpio_read(void)
@@ -164,6 +176,7 @@ static int bcm2835gpio_write(int tck, int tms, int tdi)
 
 	GPIO_SET = set;
 	GPIO_CLR = clear;
+	bcm2835_gpio_synchronize();
 
 	for (unsigned int i = 0; i < jtag_delay; i++)
 		asm volatile ("");
@@ -184,6 +197,7 @@ static int bcm2835gpio_swd_write_fast(int swclk, int swdio)
 
 	GPIO_SET = set;
 	GPIO_CLR = clear;
+	bcm2835_gpio_synchronize();
 
 	for (unsigned int i = 0; i < jtag_delay; i++)
 		asm volatile ("");
@@ -234,6 +248,7 @@ static void bcm2835_swdio_drive(bool is_output)
 		if (is_gpio_config_valid(ADAPTER_GPIO_IDX_SWDIO_DIR))
 			set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO_DIR], 0);
 	}
+	bcm2835_gpio_synchronize();
 }
 
 static int bcm2835_swdio_read(void)

src/jtag/drivers/bitbang.c

@@ -380,8 +380,6 @@ static int bitbang_swd_init(void)
 
 static void bitbang_swd_exchange(bool rnw, uint8_t buf[], unsigned int offset, unsigned int bit_cnt)
 {
-	LOG_DEBUG("bitbang_swd_exchange");
-
 	if (bitbang_interface->blink) {
 		/* FIXME: we should manage errors */
 		bitbang_interface->blink(1);
@@ -412,11 +410,9 @@ static void bitbang_swd_exchange(bool rnw, uint8_t buf[], unsigned int offset, u
 
 static int bitbang_swd_switch_seq(enum swd_special_seq seq)
 {
-	LOG_DEBUG("bitbang_swd_switch_seq");
-
 	switch (seq) {
 	case LINE_RESET:
-		LOG_DEBUG("SWD line reset");
+		LOG_DEBUG_IO("SWD line reset");
 		bitbang_swd_exchange(false, (uint8_t *)swd_seq_line_reset, 0, swd_seq_line_reset_len);
 		break;
 	case JTAG_TO_SWD:
@@ -459,7 +455,6 @@ static void swd_clear_sticky_errors(void)
 
 static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk)
 {
-	LOG_DEBUG("bitbang_swd_read_reg");
 	assert(cmd & SWD_CMD_RNW);
 
 	if (queued_retval != ERROR_OK) {
@@ -481,7 +476,7 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay
 		uint32_t data = buf_get_u32(trn_ack_data_parity_trn, 1 + 3, 32);
 		int parity = buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 32, 1);
 
-		LOG_DEBUG("%s %s read reg %X = %08"PRIx32,
+		LOG_DEBUG_IO("%s %s read reg %X = %08" PRIx32,
 			  ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
 			  cmd & SWD_CMD_APNDP ? "AP" : "DP",
 			  (cmd & SWD_CMD_A32) >> 1,
@@ -510,7 +505,6 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay
 
 static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk)
 {
-	LOG_DEBUG("bitbang_swd_write_reg");
 	assert(!(cmd & SWD_CMD_RNW));
 
 	if (queued_retval != ERROR_OK) {
@@ -537,7 +531,7 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay
 
 		int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3);
 
-		LOG_DEBUG("%s%s %s write reg %X = %08"PRIx32,
+		LOG_DEBUG_IO("%s%s %s write reg %X = %08" PRIx32,
 			  check_ack ? "" : "ack ignored ",
 			  ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
 			  cmd & SWD_CMD_APNDP ? "AP" : "DP",
@@ -562,14 +556,13 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay
 
 static int bitbang_swd_run_queue(void)
 {
-	LOG_DEBUG("bitbang_swd_run_queue");
 	/* A transaction must be followed by another transaction or at least 8 idle cycles to
 	 * ensure that data is clocked through the AP. */
 	bitbang_swd_exchange(true, NULL, 0, 8);
 
 	int retval = queued_retval;
 	queued_retval = ERROR_OK;
-	LOG_DEBUG("SWD queue return value: %02x", retval);
+	LOG_DEBUG_IO("SWD queue return value: %02x", retval);
 	return retval;
 }
 

src/jtag/drivers/cmsis_dap.c

@@ -573,6 +573,8 @@ static int cmsis_dap_metacmd_targetsel(uint32_t instance_id)
 	The purpose of this operation is to select the target
 	corresponding to the instance_id that is written */
 
+	LOG_DEBUG_IO("DP write reg TARGETSEL %" PRIx32, instance_id);
+
 	size_t idx = 0;
 	command[idx++] = CMD_DAP_SWD_SEQUENCE;
 	command[idx++] = 3;	/* sequence count */
@@ -783,7 +785,7 @@ static void cmsis_dap_swd_write_from_queue(struct cmsis_dap *dap)
 		uint8_t cmd = transfer->cmd;
 		uint32_t data = transfer->data;
 
-		LOG_DEBUG_IO("%s %s reg %x %"PRIx32,
+		LOG_DEBUG_IO("%s %s reg %x %" PRIx32,
 				cmd & SWD_CMD_APNDP ? "AP" : "DP",
 				cmd & SWD_CMD_RNW ? "read" : "write",
 			  (cmd & SWD_CMD_A32) >> 1, data);
@@ -889,7 +891,7 @@ static void cmsis_dap_swd_read_process(struct cmsis_dap *dap, int timeout_ms)
 			uint32_t tmp = data;
 			idx += 4;
 
-			LOG_DEBUG_IO("Read result: %"PRIx32, data);
+			LOG_DEBUG_IO("Read result: %" PRIx32, data);
 
 			/* Imitate posted AP reads */
 			if ((transfer->cmd & SWD_CMD_APNDP) ||

src/pld/virtex2.c

@@ -157,6 +157,8 @@ static int virtex2_load(struct pld_device *pld_device, const char *filename)
 	virtex2_set_instr(virtex2_info->tap, 0x3f);		/* BYPASS */
 	jtag_execute_queue();
 
+	xilinx_free_bit_file(&bit_file);
+
 	return ERROR_OK;
 }
 
@@ -173,7 +175,7 @@ COMMAND_HANDLER(virtex2_handle_read_stat_command)
 	device = get_pld_device_by_num(dev_id);
 	if (!device) {
 		command_print(CMD, "pld device '#%s' is out of bounds", CMD_ARGV[0]);
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	virtex2_read_stat(device, &status);
@@ -195,7 +197,7 @@ PLD_DEVICE_COMMAND_HANDLER(virtex2_pld_device_command)
 	tap = jtag_tap_by_string(CMD_ARGV[1]);
 	if (!tap) {
 		command_print(CMD, "Tap: %s does not exist", CMD_ARGV[1]);
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	virtex2_info = malloc(sizeof(struct virtex2_pld_device));

src/pld/xilinx_bit.c

@@ -87,26 +87,48 @@ int xilinx_read_bit_file(struct xilinx_bit_file *bit_file, const char *filename)
 		return ERROR_PLD_FILE_LOAD_FAILED;
 	}
 
+	bit_file->source_file = NULL;
+	bit_file->part_name = NULL;
+	bit_file->date = NULL;
+	bit_file->time = NULL;
+	bit_file->data = NULL;
+
 	read_count = fread(bit_file->unknown_header, 1, 13, input_file);
 	if (read_count != 13) {
 		LOG_ERROR("couldn't read unknown_header from file '%s'", filename);
+		fclose(input_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
 	}
 
-	if (read_section(input_file, 2, 'a', NULL, &bit_file->source_file) != ERROR_OK)
+	if (read_section(input_file, 2, 'a', NULL, &bit_file->source_file) != ERROR_OK) {
+		xilinx_free_bit_file(bit_file);
+		fclose(input_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
+	}
 
-	if (read_section(input_file, 2, 'b', NULL, &bit_file->part_name) != ERROR_OK)
+	if (read_section(input_file, 2, 'b', NULL, &bit_file->part_name) != ERROR_OK) {
+		xilinx_free_bit_file(bit_file);
+		fclose(input_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
+	}
 
-	if (read_section(input_file, 2, 'c', NULL, &bit_file->date) != ERROR_OK)
+	if (read_section(input_file, 2, 'c', NULL, &bit_file->date) != ERROR_OK) {
+		xilinx_free_bit_file(bit_file);
+		fclose(input_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
+	}
 
-	if (read_section(input_file, 2, 'd', NULL, &bit_file->time) != ERROR_OK)
+	if (read_section(input_file, 2, 'd', NULL, &bit_file->time) != ERROR_OK) {
+		xilinx_free_bit_file(bit_file);
+		fclose(input_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
+	}
 
-	if (read_section(input_file, 4, 'e', &bit_file->length, &bit_file->data) != ERROR_OK)
+	if (read_section(input_file, 4, 'e', &bit_file->length, &bit_file->data) != ERROR_OK) {
+		xilinx_free_bit_file(bit_file);
+		fclose(input_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
+	}
 
 	LOG_DEBUG("bit_file: %s %s %s,%s %" PRIu32 "", bit_file->source_file, bit_file->part_name,
 		bit_file->date, bit_file->time, bit_file->length);
@@ -115,3 +137,12 @@ int xilinx_read_bit_file(struct xilinx_bit_file *bit_file, const char *filename)
 
 	return ERROR_OK;
 }
+
+void xilinx_free_bit_file(struct xilinx_bit_file *bit_file)
+{
+	free(bit_file->source_file);
+	free(bit_file->part_name);
+	free(bit_file->date);
+	free(bit_file->time);
+	free(bit_file->data);
+}

src/pld/xilinx_bit.h

@@ -22,4 +22,6 @@ struct xilinx_bit_file {
 
 int xilinx_read_bit_file(struct xilinx_bit_file *bit_file, const char *filename);
 
+void xilinx_free_bit_file(struct xilinx_bit_file *bit_file);
+
 #endif /* OPENOCD_PLD_XILINX_BIT_H */

src/rtos/hwthread.c

@@ -78,7 +78,6 @@ static int hwthread_fill_thread(struct rtos *rtos, struct target *curr, int thre
 static int hwthread_update_threads(struct rtos *rtos)
 {
 	int threads_found = 0;
-	int thread_list_size = 0;
 	struct target_list *head;
 	struct target *target;
 	int64_t current_thread = 0;
@@ -100,13 +99,13 @@ static int hwthread_update_threads(struct rtos *rtos)
 			if (!target_was_examined(curr))
 				continue;
 
-			++thread_list_size;
+			++threads_found;
 		}
 	} else
-		thread_list_size = 1;
+		threads_found = 1;
 
 	/* create space for new thread details */
-	rtos->thread_details = malloc(sizeof(struct thread_detail) * thread_list_size);
+	rtos->thread_details = malloc(sizeof(struct thread_detail) * threads_found);
 
 	if (target->smp) {
 		/* loop over all threads */
@@ -171,13 +170,10 @@ static int hwthread_update_threads(struct rtos *rtos)
 			default:
 				break;
 			}
-
-			threads_found++;
 		}
 	} else {
 		hwthread_fill_thread(rtos, target, threads_found);
 		current_thread = threadid_from_target(target);
-		threads_found++;
 	}
 
 	rtos->thread_count = threads_found;

src/target/adi_v5_swd.c

@@ -177,6 +177,19 @@ static int swd_multidrop_select_inner(struct adiv5_dap *dap, uint32_t *dpidr_ptr
 	assert(dap_is_multidrop(dap));
 
 	swd_send_sequence(dap, LINE_RESET);
+	/* From ARM IHI 0074C ADIv6.0, chapter B4.3.3 "Connection and line reset
+	 * sequence":
+	 * - line reset sets DP_SELECT_DPBANK to zero;
+	 * - read of DP_DPIDR takes the connection out of reset;
+	 * - write of DP_TARGETSEL keeps the connection in reset;
+	 * - other accesses return protocol error (SWDIO not driven by target).
+	 *
+	 * Read DP_DPIDR to get out of reset. Initialize dap->select to zero to
+	 * skip the write to DP_SELECT, avoiding the protocol error. Set again
+	 * dap->select to DP_SELECT_INVALID because the rest of the register is
+	 * unknown after line reset.
+	 */
+	dap->select = 0;
 
 	retval = swd_queue_dp_write_inner(dap, DP_TARGETSEL, dap->multidrop_targetsel);
 	if (retval != ERROR_OK)
@@ -196,6 +209,8 @@ static int swd_multidrop_select_inner(struct adiv5_dap *dap, uint32_t *dpidr_ptr
 			return retval;
 	}
 
+	dap->select = DP_SELECT_INVALID;
+
 	retval = swd_queue_dp_read_inner(dap, DP_DLPIDR, &dlpidr);
 	if (retval != ERROR_OK)
 		return retval;
@@ -257,6 +272,8 @@ static int swd_multidrop_select(struct adiv5_dap *dap)
 
 		LOG_DEBUG("Failed to select multidrop %s, retrying...",
 				  adiv5_dap_name(dap));
+		/* we going to retry localy, do not ask for full reconnect */
+		dap->do_reconnect = false;
 	}
 
 	return retval;
@@ -342,6 +359,7 @@ static int swd_connect_single(struct adiv5_dap *dap)
 
 		dap->switch_through_dormant = !dap->switch_through_dormant;
 	} while (timeval_ms() < timeout);
+
 	dap->select = DP_SELECT_INVALID;
 
 	if (retval != ERROR_OK) {

src/target/arm_adi_v5.c

@@ -113,7 +113,7 @@ static int mem_ap_setup_tar(struct adiv5_ap *ap, target_addr_t tar)
 		int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR(ap->dap), (uint32_t)(tar & 0xffffffffUL));
 		if (retval == ERROR_OK && is_64bit_ap(ap)) {
 			/* See if bits 63:32 of tar is different from last setting */
-			if ((ap->tar_value >> 32) != (tar >> 32))
+			if (!ap->tar_valid || (ap->tar_value >> 32) != (tar >> 32))
 				retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR64(ap->dap), (uint32_t)(tar >> 32));
 		}
 		if (retval != ERROR_OK) {

src/target/armv7m.c

@@ -528,11 +528,14 @@ int armv7m_start_algorithm(struct target *target,
 
 	/* Store all non-debug execution registers to armv7m_algorithm_info context */
 	for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
+		struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
+		if (!reg->valid)
+			armv7m_get_core_reg(reg);
 
-		armv7m_algorithm_info->context[i] = buf_get_u32(
-				armv7m->arm.core_cache->reg_list[i].value,
-				0,
-				32);
+		if (!reg->valid)
+			LOG_TARGET_WARNING(target, "Storing invalid register %s", reg->name);
+
+		armv7m_algorithm_info->context[i] = buf_get_u32(reg->value, 0, 32);
 	}
 
 	for (int i = 0; i < num_mem_params; i++) {
@@ -726,8 +729,9 @@ int armv7m_arch_state(struct target *target)
 	ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
 	sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
 
-	LOG_USER("target halted due to %s, current mode: %s %s\n"
+	LOG_USER("[%s] halted due to %s, current mode: %s %s\n"
 		"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s%s",
+		target_name(target),
 		debug_reason_name(target),
 		arm_mode_name(arm->core_mode),
 		armv7m_exception_string(armv7m->exception_number),

src/target/cortex_m.c

@@ -1408,8 +1408,9 @@ static int cortex_m_assert_reset(struct target *target)
 	struct armv7m_common *armv7m = &cortex_m->armv7m;
 	enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
 
-	LOG_TARGET_DEBUG(target, "target->state: %s",
-		target_state_name(target));
+	LOG_TARGET_DEBUG(target, "target->state: %s,%s examined",
+		target_state_name(target),
+		target_was_examined(target) ? "" : " not");
 
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
 
@@ -1428,24 +1429,40 @@ static int cortex_m_assert_reset(struct target *target)
 
 	bool srst_asserted = false;
 
-	if (!target_was_examined(target)) {
-		if (jtag_reset_config & RESET_HAS_SRST) {
-			adapter_assert_reset();
-			if (target->reset_halt)
-				LOG_TARGET_ERROR(target, "Target not examined, will not halt after reset!");
-			return ERROR_OK;
-		} else {
-			LOG_TARGET_ERROR(target, "Target not examined, reset NOT asserted!");
-			return ERROR_FAIL;
-		}
-	}
-
 	if ((jtag_reset_config & RESET_HAS_SRST) &&
-	    (jtag_reset_config & RESET_SRST_NO_GATING)) {
+		((jtag_reset_config & RESET_SRST_NO_GATING) || !armv7m->debug_ap)) {
+		/* If we have no debug_ap, asserting SRST is the only thing
+		 * we can do now */
 		adapter_assert_reset();
 		srst_asserted = true;
 	}
 
+	/* TODO: replace the hack calling target_examine_one()
+	 * as soon as a better reset framework is available */
+	if (!target_was_examined(target) && !target->defer_examine
+		&& srst_asserted && (jtag_reset_config & RESET_SRST_NO_GATING)) {
+		LOG_TARGET_DEBUG(target, "Trying to re-examine under reset");
+		target_examine_one(target);
+	}
+
+	/* We need at least debug_ap to go further.
+	 * Inform user and bail out if we don't have one. */
+	if (!armv7m->debug_ap) {
+		if (srst_asserted) {
+			if (target->reset_halt)
+				LOG_TARGET_ERROR(target, "Debug AP not available, will not halt after reset!");
+
+			/* Do not propagate error: reset was asserted, proceed to deassert! */
+			target->state = TARGET_RESET;
+			register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
+			return ERROR_OK;
+
+		} else {
+			LOG_TARGET_ERROR(target, "Debug AP not available, reset NOT asserted!");
+			return ERROR_FAIL;
+		}
+	}
+
 	/* Enable debug requests */
 	int retval = cortex_m_read_dhcsr_atomic_sticky(target);
 
@@ -1546,7 +1563,7 @@ static int cortex_m_assert_reset(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 
-	if (target->reset_halt) {
+	if (target->reset_halt && target_was_examined(target)) {
 		retval = target_halt(target);
 		if (retval != ERROR_OK)
 			return retval;
@@ -1559,8 +1576,9 @@ static int cortex_m_deassert_reset(struct target *target)
 {
 	struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
 
-	LOG_TARGET_DEBUG(target, "target->state: %s",
-		target_state_name(target));
+	LOG_TARGET_DEBUG(target, "target->state: %s,%s examined",
+		target_state_name(target),
+		target_was_examined(target) ? "" : " not");
 
 	/* deassert reset lines */
 	adapter_deassert_reset();
@@ -1568,8 +1586,8 @@ static int cortex_m_deassert_reset(struct target *target)
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
 
 	if ((jtag_reset_config & RESET_HAS_SRST) &&
-	    !(jtag_reset_config & RESET_SRST_NO_GATING) &&
-		target_was_examined(target)) {
+		!(jtag_reset_config & RESET_SRST_NO_GATING) &&
+		armv7m->debug_ap) {
 
 		int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
 		if (retval != ERROR_OK) {

src/target/dsp563xx.c

@@ -2140,7 +2140,7 @@ COMMAND_HANDLER(dsp563xx_mem_command)
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], count);
 	}
 
-	buffer = calloc(count, sizeof(uint32_t));
+	buffer = calloc(count, 4);
 
 	if (read_mem == 1) {
 		err = dsp563xx_read_memory(target, mem_type, address, sizeof(uint32_t),

src/target/espressif/esp32s2.c

@@ -402,6 +402,8 @@ static int esp32s2_poll(struct target *target)
 {
 	enum target_state old_state = target->state;
 	int ret = esp_xtensa_poll(target);
+	if (ret != ERROR_OK)
+		return ret;
 
 	if (old_state != TARGET_HALTED && target->state == TARGET_HALTED) {
 		/* Call any event callbacks that are applicable */

src/target/hla_target.c

@@ -347,6 +347,13 @@ static int hl_assert_reset(struct target *target)
 
 	adapter->layout->api->write_debug_reg(adapter->handle, DCB_DHCSR, DBGKEY|C_DEBUGEN);
 
+	if (!target_was_examined(target) && !target->defer_examine
+		&& srst_asserted && res == ERROR_OK) {
+		/* If the target is not examined, now under reset it is good time to retry examination */
+		LOG_TARGET_DEBUG(target, "Trying to re-examine under reset");
+		target_examine_one(target);
+	}
+
 	/* only set vector catch if halt is requested */
 	if (target->reset_halt)
 		adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA|VC_CORERESET);

src/target/riscv/riscv-013.c

@@ -2359,9 +2359,7 @@ static int assert_reset(struct target *target)
 		/* TODO: Try to use hasel in dmcontrol */
 
 		/* Set haltreq for each hart. */
-		uint32_t control = control_base;
-
-		control = set_hartsel(control_base, target->coreid);
+		uint32_t control = set_hartsel(control_base, target->coreid);
 		control = set_field(control, DM_DMCONTROL_HALTREQ,
 				target->reset_halt ? 1 : 0);
 		dmi_write(target, DM_DMCONTROL, control);
@@ -4463,7 +4461,9 @@ static int riscv013_test_sba_config_reg(struct target *target,
 
 	uint32_t rd_val;
 	uint32_t sbcs_orig;
-	dmi_read(target, &sbcs_orig, DM_SBCS);
+	int retval = dmi_read(target, &sbcs_orig, DM_SBCS);
+	if (retval != ERROR_OK)
+		return retval;
 
 	uint32_t sbcs = sbcs_orig;
 	bool test_passed;

src/target/riscv/riscv.c

@@ -453,10 +453,7 @@ static int riscv_init_target(struct command_context *cmd_ctx,
 	if (bscan_tunnel_ir_width != 0) {
 		assert(target->tap->ir_length >= 6);
 		uint32_t ir_user4_raw = 0x23 << (target->tap->ir_length - 6);
-		ir_user4[0] = (uint8_t)ir_user4_raw;
-		ir_user4[1] = (uint8_t)(ir_user4_raw >>= 8);
-		ir_user4[2] = (uint8_t)(ir_user4_raw >>= 8);
-		ir_user4[3] = (uint8_t)(ir_user4_raw >>= 8);
+		h_u32_to_le(ir_user4, ir_user4_raw);
 		select_user4.num_bits = target->tap->ir_length;
 		bscan_tunneled_ir_width[0] = bscan_tunnel_ir_width;
 		if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
@@ -713,7 +710,6 @@ static int add_trigger(struct target *target, struct trigger *trigger)
 			return result;
 		int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
 
-		result = ERROR_OK;
 		switch (type) {
 			case 1:
 				result = maybe_add_trigger_t1(target, trigger, tdata1);
@@ -1611,6 +1607,7 @@ static int riscv_address_translate(struct target *target,
 	LOG_DEBUG("virtual=0x%" TARGET_PRIxADDR "; mode=%s", virtual, info->name);
 
 	/* verify bits xlen-1:va_bits-1 are all equal */
+	assert(xlen >= info->va_bits);
 	target_addr_t mask = ((target_addr_t)1 << (xlen - (info->va_bits - 1))) - 1;
 	target_addr_t masked_msbs = (virtual >> (info->va_bits - 1)) & mask;
 	if (masked_msbs != 0 && masked_msbs != mask) {
@@ -2669,27 +2666,25 @@ COMMAND_HANDLER(riscv_authdata_write)
 	uint32_t value;
 	unsigned int index = 0;
 
-	if (CMD_ARGC == 0) {
-		/* nop */
-	} else if (CMD_ARGC == 1) {
+	if (CMD_ARGC == 0 || CMD_ARGC > 2)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	if (CMD_ARGC == 1) {
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
-	} else if (CMD_ARGC == 2) {
+	} else {
 		COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index);
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
-	} else {
-		LOG_ERROR("Command takes at most 2 arguments");
-		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	struct target *target = get_current_target(CMD_CTX);
 	RISCV_INFO(r);
 
-	if (r->authdata_write) {
-		return r->authdata_write(target, value, index);
-	} else {
+	if (!r->authdata_write) {
 		LOG_ERROR("authdata_write is not implemented for this target.");
 		return ERROR_FAIL;
 	}
+
+	return r->authdata_write(target, value, index);
 }
 
 COMMAND_HANDLER(riscv_dmi_read)
@@ -2749,6 +2744,9 @@ COMMAND_HANDLER(riscv_dmi_write)
 
 COMMAND_HANDLER(riscv_test_sba_config_reg)
 {
+	LOG_WARNING("Command \"riscv test_sba_config_reg\" is deprecated. "
+		"It will be removed in a future OpenOCD version.");
+
 	if (CMD_ARGC != 4) {
 		LOG_ERROR("Command takes exactly 4 arguments");
 		return ERROR_COMMAND_SYNTAX_ERROR;

src/target/startup.tcl

@@ -114,10 +114,21 @@ proc ocd_process_reset_inner { MODE } {
 				continue
 			}
 
-			# don't wait for targets where examination is deferred
-			# they can not be halted anyway at this point
-			if { ![$t was_examined] && [$t examine_deferred] } {
-				continue
+			if { ![$t was_examined] } {
+				# don't wait for targets where examination is deferred
+				# they can not be halted anyway at this point
+				if { [$t examine_deferred] } {
+					continue
+				}
+				# try to re-examine or target state will be unknown
+				$t invoke-event examine-start
+				set err [catch "$t arp_examine allow-defer"]
+				if { $err } {
+					$t invoke-event examine-fail
+					return -code error [format "TARGET: %s - Not examined" $t]
+				} else {
+					$t invoke-event examine-end
+				}
 			}
 
 			# Wait up to 1 second for target to halt. Why 1sec? Cause

src/target/target.c

@@ -4717,7 +4717,7 @@ static int target_jim_read_memory(Jim_Interp *interp, int argc,
 				break;
 			}
 
-			char value_buf[11];
+			char value_buf[19];
 			snprintf(value_buf, sizeof(value_buf), "0x%" PRIx64, v);
 
 			Jim_ListAppendElement(interp, result_list,

src/target/xtensa/xtensa.c

@@ -168,8 +168,9 @@
 #define XT_REG_A3         (xtensa_regs[XT_REG_IDX_AR3].reg_num)
 #define XT_REG_A4         (xtensa_regs[XT_REG_IDX_AR4].reg_num)
 
-#define XT_PS_REG_NUM_BASE          (0xc0U)	/* (EPS2 - 2), for adding DBGLEVEL */
-#define XT_PC_REG_NUM_BASE          (0xb0U)	/* (EPC1 - 1), for adding DBGLEVEL */
+#define XT_PS_REG_NUM               (0xe6U)
+#define XT_EPS_REG_NUM_BASE         (0xc0U)	/* (EPS2 - 2), for adding DBGLEVEL */
+#define XT_EPC_REG_NUM_BASE         (0xb0U)	/* (EPC1 - 1), for adding DBGLEVEL */
 #define XT_PC_REG_NUM_VIRTUAL       (0xffU)	/* Marker for computing PC (EPC[DBGLEVEL) */
 #define XT_PC_DBREG_NUM_BASE        (0x20U)	/* External (i.e., GDB) access */
 
@@ -245,7 +246,7 @@ struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS] = {
 	XT_MK_REG_DESC("ar63", 0x3F, XT_REG_GENERAL, 0),
 	XT_MK_REG_DESC("windowbase", 0x48, XT_REG_SPECIAL, 0),
 	XT_MK_REG_DESC("windowstart", 0x49, XT_REG_SPECIAL, 0),
-	XT_MK_REG_DESC("ps", 0xE6, XT_REG_SPECIAL, 0),	/* PS (not mapped through EPS[]) */
+	XT_MK_REG_DESC("ps", XT_PS_REG_NUM, XT_REG_SPECIAL, 0),	/* PS (not mapped through EPS[]) */
 	XT_MK_REG_DESC("ibreakenable", 0x60, XT_REG_SPECIAL, 0),
 	XT_MK_REG_DESC("ddr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD),
 	XT_MK_REG_DESC("ibreaka0", 0x80, XT_REG_SPECIAL, 0),
@@ -630,7 +631,7 @@ static int xtensa_write_dirty_registers(struct target *target)
 							/* reg number of PC for debug interrupt depends on NDEBUGLEVEL
 							 **/
 							reg_num =
-								(XT_PC_REG_NUM_BASE +
+								(XT_EPC_REG_NUM_BASE +
 								xtensa->core_config->debug.irq_level);
 						xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, reg_num, XT_REG_A3));
 					}
@@ -1105,10 +1106,10 @@ int xtensa_fetch_all_regs(struct target *target)
 			case XT_REG_SPECIAL:
 				if (reg_num == XT_PC_REG_NUM_VIRTUAL) {
 					/* reg number of PC for debug interrupt depends on NDEBUGLEVEL */
-					reg_num = (XT_PC_REG_NUM_BASE + xtensa->core_config->debug.irq_level);
+					reg_num = XT_EPC_REG_NUM_BASE + xtensa->core_config->debug.irq_level;
 				} else if (reg_num == xtensa_regs[XT_REG_IDX_PS].reg_num) {
 					/* reg number of PS for debug interrupt depends on NDEBUGLEVEL */
-					reg_num = (XT_PS_REG_NUM_BASE + xtensa->core_config->debug.irq_level);
+					reg_num = XT_EPS_REG_NUM_BASE + xtensa->core_config->debug.irq_level;
 				} else if (reg_num == xtensa_regs[XT_REG_IDX_CPENABLE].reg_num) {
 					/* CPENABLE already read/updated; don't re-read */
 					reg_fetched = false;
@@ -1629,7 +1630,6 @@ int xtensa_do_step(struct target *target, int current, target_addr_t address, in
 
 	target->debug_reason = DBG_REASON_SINGLESTEP;
 	target->state = TARGET_HALTED;
-	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 	LOG_DEBUG("Done stepping, PC=%" PRIX32, cur_pc);
 
 	if (cause & DEBUGCAUSE_DB) {
@@ -1657,7 +1657,12 @@ int xtensa_do_step(struct target *target, int current, target_addr_t address, in
 
 int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
 {
-	return xtensa_do_step(target, current, address, handle_breakpoints);
+	int retval = xtensa_do_step(target, current, address, handle_breakpoints);
+	if (retval != ERROR_OK)
+		return retval;
+	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+
+	return ERROR_OK;
 }
 
 /**
@@ -1738,15 +1743,12 @@ int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t si
 		}
 	}
 
-	if (addrstart_al == address && addrend_al == address + (size * count)) {
-		albuff = buffer;
-	} else {
-		albuff = malloc(addrend_al - addrstart_al);
-		if (!albuff) {
-			LOG_TARGET_ERROR(target, "Out of memory allocating %" TARGET_PRIdADDR " bytes!",
-				addrend_al - addrstart_al);
-			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-		}
+	unsigned int alloc_bytes = ALIGN_UP(addrend_al - addrstart_al, sizeof(uint32_t));
+	albuff = calloc(alloc_bytes, 1);
+	if (!albuff) {
+		LOG_TARGET_ERROR(target, "Out of memory allocating %" PRId64 " bytes!",
+			addrend_al - addrstart_al);
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
 	/* We're going to use A3 here */
@@ -1783,9 +1785,9 @@ int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t si
 	if (res != ERROR_OK) {
 		if (xtensa->probe_lsddr32p != 0) {
 			/* Disable fast memory access instructions and retry before reporting an error */
-			LOG_TARGET_INFO(target, "Disabling LDDR32.P/SDDR32.P");
+			LOG_TARGET_DEBUG(target, "Disabling LDDR32.P/SDDR32.P");
 			xtensa->probe_lsddr32p = 0;
-			res = xtensa_read_memory(target, address, size, count, buffer);
+			res = xtensa_read_memory(target, address, size, count, albuff);
 			bswap = false;
 		} else {
 			LOG_TARGET_WARNING(target, "Failed reading %d bytes at address "TARGET_ADDR_FMT,
@@ -1795,11 +1797,8 @@ int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t si
 
 	if (bswap)
 		buf_bswap32(albuff, albuff, addrend_al - addrstart_al);
-	if (albuff != buffer) {
-		memcpy(buffer, albuff + (address & 3), (size * count));
-		free(albuff);
-	}
-
+	memcpy(buffer, albuff + (address & 3), (size * count));
+	free(albuff);
 	return res;
 }
 
@@ -1855,7 +1854,7 @@ int xtensa_write_memory(struct target *target,
 		albuff = malloc(addrend_al - addrstart_al);
 	}
 	if (!albuff) {
-		LOG_TARGET_ERROR(target, "Out of memory allocating %" TARGET_PRIdADDR " bytes!",
+		LOG_TARGET_ERROR(target, "Out of memory allocating %" PRId64 " bytes!",
 			addrend_al - addrstart_al);
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
@@ -2508,6 +2507,12 @@ static int xtensa_build_reg_cache(struct target *target)
 			unsigned int j;
 			for (j = 0; j < reg_cache->num_regs; j++) {
 				if (!strcmp(reg_cache->reg_list[j].name, xtensa->contiguous_regs_desc[i]->name)) {
+					/*	Register number field is not filled above.
+						Here we are assigning the corresponding index from the contiguous reg list.
+						These indexes are in the same order with gdb g-packet request/response.
+						Some more changes may be required for sparse reg lists.
+					*/
+					reg_cache->reg_list[j].number = i;
 					xtensa->contiguous_regs_list[i] = &(reg_cache->reg_list[j]);
 					LOG_TARGET_DEBUG(target,
 						"POPULATE contiguous regs list: %-16s, dbreg_num 0x%04x",
@@ -3447,8 +3452,8 @@ COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa)
 		else
 			rptr->flags = 0;
 
-		if ((rptr->reg_num == (XT_PS_REG_NUM_BASE + xtensa->core_config->debug.irq_level)) &&
-			(xtensa->core_config->core_type == XT_LX) && (rptr->type == XT_REG_SPECIAL)) {
+		if (rptr->reg_num == (XT_EPS_REG_NUM_BASE + xtensa->core_config->debug.irq_level) &&
+			xtensa->core_config->core_type == XT_LX && rptr->type == XT_REG_SPECIAL) {
 			xtensa->eps_dbglevel_idx = XT_NUM_REGS + xtensa->num_optregs - 1;
 			LOG_DEBUG("Setting PS (%s) index to %d", rptr->name, xtensa->eps_dbglevel_idx);
 		}

tcl/target/rp2040-core0.cfg

@@ -1,5 +1,17 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
+# RP2040 is a microcontroller with dual Cortex-M0+ core.
+# https://www.raspberrypi.com/documentation/microcontrollers/rp2040.html
+
+# The device requires multidrop SWD for debug.
+# This configuration file is intended for a special adapter
+# which selects a multidrop target on its own.
+# Cannot be used with a standard SWD adapter!
+
+echo "Warn : rp2040-core0.cfg configuration file is deprecated and will be"
+echo "       removed in the next release. Use following parameters instead:"
+echo "          -c 'set USE_CORE 0' -f target/rp2040.cfg"
+
 transport select swd
 
 source [find target/swj-dp.tcl]
@@ -26,7 +38,10 @@ swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
-$_TARGETNAME configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE
+
+# Backup the work area. The flash probe runs an algorithm on the target CPU.
+# The flash is probed during gdb connect if gdb_memory_map is enabled (by default).
+$_TARGETNAME configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1
 
 set _FLASHNAME $_CHIPNAME.flash
 set _FLASHSIZE 0x200000

tcl/target/rp2040.cfg

@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# RP2040 is a microcontroller with dual Cortex-M0+ core.
+# https://www.raspberrypi.com/documentation/microcontrollers/rp2040.html
+
+# The device requires multidrop SWD for debug.
+transport select swd
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME rp2040
+}
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x10000
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x01002927
+}
+
+# Set to '0' or '1' for single core configuration,
+# anything else for isolated debugging of both cores
+if { [info exists USE_CORE] } {
+	set _USE_CORE $USE_CORE
+} else {
+	set _USE_CORE { 0 1 }
+}
+set _BOTH_CORES [expr { $_USE_CORE != 0 && $_USE_CORE != 1 }]
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+# core 0
+if { $_USE_CORE != 1 } {
+	dap create $_CHIPNAME.dap0 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0
+	set _TARGETNAME_0 $_CHIPNAME.core0
+	target create $_TARGETNAME_0 cortex_m -dap $_CHIPNAME.dap0 -coreid 0
+	# srst does not exist; use SYSRESETREQ to perform a soft reset
+	$_TARGETNAME_0 cortex_m reset_config sysresetreq
+}
+
+# core 1
+if { $_USE_CORE != 0 } {
+	dap create $_CHIPNAME.dap1 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 1
+	set _TARGETNAME_1 $_CHIPNAME.core1
+	target create $_TARGETNAME_1 cortex_m -dap $_CHIPNAME.dap1 -coreid 1
+	$_TARGETNAME_1 cortex_m reset_config sysresetreq
+}
+
+if { $_USE_CORE == 1 } {
+	set _FLASH_TARGET $_TARGETNAME_1
+} else {
+	set _FLASH_TARGET $_TARGETNAME_0
+}
+# Backup the work area. The flash probe runs an algorithm on the target CPU.
+# The flash is probed during gdb connect if gdb_memory_map is enabled (by default).
+$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME rp2040_flash 0x10000000 0 0 0 $_FLASH_TARGET
+
+if { $_BOTH_CORES } {
+	# Alias to ensure gdb connecting to core 1 gets the correct memory map
+	flash bank $_CHIPNAME.alias virtual 0x10000000 0 0 0 $_TARGETNAME_1 $_FLASHNAME
+
+	# Select core 0
+	targets $_TARGETNAME_0
+}

tcl/target/stm32x5x_common.cfg

@@ -58,7 +58,9 @@ if {[using_jtag]} {
 
 reset_config srst_nogate
 
-if {![using_hla]} {
+if {[using_hla]} {
+	echo "Warn : The selected adapter does not support debugging this device in secure mode"
+} else {
 	# if srst is not fitted use SYSRESETREQ to
 	# perform a soft reset
 	cortex_m reset_config sysresetreq
@@ -71,13 +73,18 @@ proc stm32x5x_is_secure {} {
 }
 
 proc stm32x5x_ahb_ap_non_secure_access {} {
-	# SPROT=1=Non Secure access, Priv=1
-	[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
+	# in HLA mode, non-secure debugging is possible without changing the AP CSW
+	if {![using_hla]} {
+		# SPROT=1=Non Secure access, Priv=1
+		[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
+	}
 }
 
 proc stm32x5x_ahb_ap_secure_access {} {
-	# SPROT=0=Secure access, Priv=1
-	[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
+	if {![using_hla]} {
+		# SPROT=0=Secure access, Priv=1
+		[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
+	}
 }
 
 $_TARGETNAME configure -event reset-start {
@@ -152,10 +159,11 @@ lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
 proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
 	targets $_targetname
 
-	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
-	# change this value accordingly to configure trace pins
+	# Set TRACE_EN and TRACE_IOEN in DBGMCU_CR
+	# Leave TRACE_MODE untouched (defaults to async).
+	# When using sync change this value accordingly to configure trace pins
 	# assignment
-	mmw 0xE0044004 0x00000020 0
+	mmw 0xE0044004 0x00000030 0
 }
 
 $_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"

tcl/target/ti_k3.cfg

@@ -12,6 +12,8 @@
 #  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
 #
 
+source [find target/swj-dp.tcl]
+
 if { [info exists SOC] } {
 	set _soc $SOC
 } else {
@@ -164,7 +166,8 @@ switch $_soc {
 	}
 }
 
-jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
+
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu

tcl/target/xtensa-core-esp32.cfg

@@ -22,6 +22,7 @@ xtensa xtmem	irom				0x40000000	0x64F00
 xtensa xtmem	iram				0x40070000	0x30000
 xtensa xtmem	iram				0x400C0000	0x2000
 xtensa xtmem	drom				0x3F400000	0x800000
+xtensa xtmem	drom				0x3FF90000	0x10000
 xtensa xtmem	dram				0x3FFAE000	0x52000
 xtensa xtmem	dram				0x3FF80000	0x2000
 xtensa xtmem	dram				0x3F800000	0x400000
@@ -35,7 +36,7 @@ xtensa xtmem	dram				0x60000000	0x20000000
 xtensa xtopt	debuglevel			6
 xtensa xtopt	ibreaknum			2
 xtensa xtopt	dbreaknum			2
-xtensa xtopt	tracemem			8192
+xtensa xtopt	tracemem			0x4000
 xtensa xtopt	tracememrev			1
 xtensa xtopt	perfcount			2
 
@@ -46,7 +47,7 @@ xtensa xtopt	perfcount			2
 #				in "Read General Registers" (g-packet) requests.
 #				NOTE: For contiguous format, registers listed in GDB order.
 #  xtregs:		Total number of Xtensa registers in the system
-xtensa xtregs	205
+xtensa xtregs	173
 xtensa xtregfmt	contiguous			105
 xtensa xtreg	pc					0x0020
 xtensa xtreg	ar0					0x0100
@@ -123,8 +124,6 @@ xtensa xtreg	configid0			0x02b0
 xtensa xtreg	configid1			0x02d0
 xtensa xtreg	ps					0x02e6
 xtensa xtreg	threadptr			0x03e7
-
-# added by hand for esp32
 xtensa xtreg	br					0x0204
 xtensa xtreg	scompare1			0x020c
 xtensa xtreg	acclo				0x0210
@@ -155,13 +154,10 @@ xtensa xtreg	f14					0x003e
 xtensa xtreg	f15					0x003f
 xtensa xtreg	fcr					0x03e8
 xtensa xtreg	fsr					0x03e9
-
 xtensa xtreg	mmid				0x0259
 xtensa xtreg	ibreakenable		0x0260
-
 xtensa xtreg	memctl				0x0261
 xtensa xtreg	atomctl				0x0263
-
 xtensa xtreg	ddr					0x0268
 xtensa xtreg	ibreaka0			0x0280
 xtensa xtreg	ibreaka1			0x0281
@@ -226,35 +222,3 @@ xtensa xtreg	a12					0x000c
 xtensa xtreg	a13					0x000d
 xtensa xtreg	a14					0x000e
 xtensa xtreg	a15					0x000f
-xtensa xtreg	pwrctl				0x2028
-xtensa xtreg	pwrstat				0x2029
-xtensa xtreg	eristat				0x202a
-xtensa xtreg	cs_itctrl			0x202b
-xtensa xtreg	cs_claimset			0x202c
-xtensa xtreg	cs_claimclr			0x202d
-xtensa xtreg	cs_lockaccess		0x202e
-xtensa xtreg	cs_lockstatus		0x202f
-xtensa xtreg	cs_authstatus		0x2030
-xtensa xtreg	fault_info			0x203f
-xtensa xtreg	trax_id				0x2040
-xtensa xtreg	trax_control		0x2041
-xtensa xtreg	trax_status			0x2042
-xtensa xtreg	trax_data			0x2043
-xtensa xtreg	trax_address		0x2044
-xtensa xtreg	trax_pctrigger		0x2045
-xtensa xtreg	trax_pcmatch		0x2046
-xtensa xtreg	trax_delay			0x2047
-xtensa xtreg	trax_memstart		0x2048
-xtensa xtreg	trax_memend			0x2049
-xtensa xtreg	pmg					0x2057
-xtensa xtreg	pmpc				0x2058
-xtensa xtreg	pm0					0x2059
-xtensa xtreg	pm1					0x205a
-xtensa xtreg	pmctrl0				0x2061
-xtensa xtreg	pmctrl1				0x2062
-xtensa xtreg	pmstat0				0x2069
-xtensa xtreg	pmstat1				0x206a
-xtensa xtreg	ocdid				0x2071
-xtensa xtreg	ocd_dcrclr			0x2072
-xtensa xtreg	ocd_dcrset			0x2073
-xtensa xtreg	ocd_dsr				0x2074

tcl/target/xtensa-core-esp32s2.cfg

@@ -23,6 +23,7 @@ xtensa xtmem	iram				0x40020000	0x50000
 xtensa xtmem	iram				0x40070000	0x2000
 xtensa xtmem	drom				0x3F000000	0x400000
 xtensa xtmem	drom				0x3F4D3FFC	0xAAC004
+xtensa xtmem	drom				0x3FFA0000	0x10000
 xtensa xtmem	dram				0x3FFB0000	0x50000
 xtensa xtmem	dram				0x3FF9E000	0x2000
 xtensa xtmem	dram				0x50000000	0x2000
@@ -36,8 +37,8 @@ xtensa xtmem	dram				0x60000000	0x20000000
 xtensa xtopt	debuglevel			6
 xtensa xtopt	ibreaknum			2
 xtensa xtopt	dbreaknum			2
-xtensa xtopt	tracemem			8192
-xtensa xtopt	tracememrev			1
+xtensa xtopt	tracemem			0x4000
+xtensa xtopt	tracememrev			0
 xtensa xtopt	perfcount			2
 
 #  Core Registers
@@ -48,7 +49,7 @@ xtensa xtopt	perfcount			2
 #				NOTE: For contiguous format, registers listed in GDB order.
 #  xtregs:		Total number of Xtensa registers in the system
 xtensa xtregs	171
-xtensa xtregfmt	contiguous			72
+xtensa xtregfmt	contiguous			73
 xtensa xtreg	pc					0x0020
 xtensa xtreg	ar0					0x0100
 xtensa xtreg	ar1					0x0101
@@ -121,8 +122,7 @@ xtensa xtreg	configid0			0x02b0
 xtensa xtreg	configid1			0x02d0
 xtensa xtreg	ps					0x02e6
 xtensa xtreg	threadptr			0x03e7
-# gpio_out should be 0x0300? Hits an exception on wrover
-xtensa xtreg	gpio_out			0x0268
+xtensa xtreg	gpio_out			0x0300
 xtensa xtreg	mmid				0x0259
 xtensa xtreg	ibreakenable		0x0260
 xtensa xtreg	ddr					0x0268
@@ -173,6 +173,38 @@ xtensa xtreg	misc0				0x02f4
 xtensa xtreg	misc1				0x02f5
 xtensa xtreg	misc2				0x02f6
 xtensa xtreg	misc3				0x02f7
+xtensa xtreg	pwrctl				0x2014
+xtensa xtreg	pwrstat				0x2015
+xtensa xtreg	eristat				0x2016
+xtensa xtreg	cs_itctrl			0x2017
+xtensa xtreg	cs_claimset			0x2018
+xtensa xtreg	cs_claimclr			0x2019
+xtensa xtreg	cs_lockaccess		0x201a
+xtensa xtreg	cs_lockstatus		0x201b
+xtensa xtreg	cs_authstatus		0x201c
+xtensa xtreg	fault_info			0x202b
+xtensa xtreg	trax_id				0x202c
+xtensa xtreg	trax_control		0x202d
+xtensa xtreg	trax_status			0x202e
+xtensa xtreg	trax_data			0x202f
+xtensa xtreg	trax_address		0x2030
+xtensa xtreg	trax_pctrigger		0x2031
+xtensa xtreg	trax_pcmatch		0x2032
+xtensa xtreg	trax_delay			0x2033
+xtensa xtreg	trax_memstart		0x2034
+xtensa xtreg	trax_memend			0x2035
+xtensa xtreg	pmg					0x2043
+xtensa xtreg	pmpc				0x2044
+xtensa xtreg	pm0					0x2045
+xtensa xtreg	pm1					0x2046
+xtensa xtreg	pmctrl0				0x2047
+xtensa xtreg	pmctrl1				0x2048
+xtensa xtreg	pmstat0				0x2049
+xtensa xtreg	pmstat1				0x204a
+xtensa xtreg	ocdid				0x204b
+xtensa xtreg	ocd_dcrclr			0x204c
+xtensa xtreg	ocd_dcrset			0x204d
+xtensa xtreg	ocd_dsr				0x204e
 xtensa xtreg	a0					0x0000
 xtensa xtreg	a1					0x0001
 xtensa xtreg	a2					0x0002
@@ -189,35 +221,3 @@ xtensa xtreg	a12					0x000c
 xtensa xtreg	a13					0x000d
 xtensa xtreg	a14					0x000e
 xtensa xtreg	a15					0x000f
-xtensa xtreg	pwrctl				0x2028
-xtensa xtreg	pwrstat				0x2029
-xtensa xtreg	eristat				0x202a
-xtensa xtreg	cs_itctrl			0x202b
-xtensa xtreg	cs_claimset			0x202c
-xtensa xtreg	cs_claimclr			0x202d
-xtensa xtreg	cs_lockaccess		0x202e
-xtensa xtreg	cs_lockstatus		0x202f
-xtensa xtreg	cs_authstatus		0x2030
-xtensa xtreg	fault_info			0x203f
-xtensa xtreg	trax_id				0x2040
-xtensa xtreg	trax_control		0x2041
-xtensa xtreg	trax_status			0x2042
-xtensa xtreg	trax_data			0x2043
-xtensa xtreg	trax_address		0x2044
-xtensa xtreg	trax_pctrigger		0x2045
-xtensa xtreg	trax_pcmatch		0x2046
-xtensa xtreg	trax_delay			0x2047
-xtensa xtreg	trax_memstart		0x2048
-xtensa xtreg	trax_memend			0x2049
-xtensa xtreg	pmg					0x2057
-xtensa xtreg	pmpc				0x2058
-xtensa xtreg	pm0					0x2059
-xtensa xtreg	pm1					0x205a
-xtensa xtreg	pmctrl0				0x2061
-xtensa xtreg	pmctrl1				0x2062
-xtensa xtreg	pmstat0				0x2069
-xtensa xtreg	pmstat1				0x206a
-xtensa xtreg	ocdid				0x2071
-xtensa xtreg	ocd_dcrclr			0x2072
-xtensa xtreg	ocd_dcrset			0x2073
-xtensa xtreg	ocd_dsr				0x2074

tcl/target/xtensa-core-esp32s3.cfg

@@ -20,6 +20,7 @@ xtensa xtmem	irom				0x40000000	0x60000
 xtensa xtmem	iram				0x40370000	0x70000
 xtensa xtmem	iram				0x600FE000	0x2000
 xtensa xtmem	drom				0x3C000000	0x1000000
+xtensa xtmem	drom				0x3FF00000	0x20000
 xtensa xtmem	dram				0x3FC88000	0x78000
 xtensa xtmem	dram				0x600FE000	0x2000
 xtensa xtmem	dram				0x50000000	0x2000
@@ -31,8 +32,8 @@ xtensa xtmem	dram				0x60000000	0x10000000
 xtensa xtopt	debuglevel			6
 xtensa xtopt	ibreaknum			2
 xtensa xtopt	dbreaknum			2
-xtensa xtopt	tracemem			16384
-xtensa xtopt	tracememrev			1
+xtensa xtopt	tracemem			0x4000
+xtensa xtopt	tracememrev			0
 xtensa xtopt	perfcount			2
 
 
@@ -43,7 +44,7 @@ xtensa xtopt	perfcount			2
 #				in "Read General Registers" (g-packet) requests.
 #				NOTE: For contiguous format, registers listed in GDB order.
 #  xtregs:		Total number of Xtensa registers in the system
-xtensa xtregs	244
+xtensa xtregs	228
 xtensa xtregfmt	contiguous			128
 xtensa xtreg	pc					0x0020
 xtensa xtreg	ar0					0x0100
@@ -128,10 +129,7 @@ xtensa xtreg	m0					0x0220
 xtensa xtreg	m1					0x0221
 xtensa xtreg	m2					0x0222
 xtensa xtreg	m3					0x0223
-
-# TODO: update gpioout address while testing on S3 HW
-xtensa xtreg	gpioout				0x02f4
-
+xtensa xtreg	gpio_out			0x030c
 xtensa xtreg	f0					0x0030
 xtensa xtreg	f1					0x0031
 xtensa xtreg	f2					0x0032
@@ -150,35 +148,32 @@ xtensa xtreg	f14					0x003e
 xtensa xtreg	f15					0x003f
 xtensa xtreg	fcr					0x03e8
 xtensa xtreg	fsr					0x03e9
-
-# TODO: update TIE state
-xtensa xtreg	accx_0				0x02f4
-xtensa xtreg	accx_1				0x02f4
-xtensa xtreg	qacc_h_0			0x02f4
-xtensa xtreg	qacc_h_1			0x02f4
-xtensa xtreg	qacc_h_2			0x02f4
-xtensa xtreg	qacc_h_3			0x02f4
-xtensa xtreg	qacc_h_4			0x02f4
-xtensa xtreg	qacc_l_0			0x02f4
-xtensa xtreg	qacc_l_1			0x02f4
-xtensa xtreg	qacc_l_2			0x02f4
-xtensa xtreg	qacc_l_3			0x02f4
-xtensa xtreg	qacc_l_4			0x02f4
-xtensa xtreg	sar_byte			0x02f4
-xtensa xtreg	fft_bit_width		0x02f4
-xtensa xtreg	ua_state_0			0x02f4
-xtensa xtreg	ua_state_1			0x02f4
-xtensa xtreg	ua_state_2			0x02f4
-xtensa xtreg	ua_state_3			0x02f4
-xtensa xtreg	q0					0x02f4
-xtensa xtreg	q1					0x02f4
-xtensa xtreg	q2					0x02f4
-xtensa xtreg	q3					0x02f4
-xtensa xtreg	q4					0x02f4
-xtensa xtreg	q5					0x02f4
-xtensa xtreg	q6					0x02f4
-xtensa xtreg	q7					0x02f4
-
+xtensa xtreg	accx_0				0x0300
+xtensa xtreg	accx_1				0x0301
+xtensa xtreg	qacc_h_0			0x0302
+xtensa xtreg	qacc_h_1			0x0303
+xtensa xtreg	qacc_h_2			0x0304
+xtensa xtreg	qacc_h_3			0x0305
+xtensa xtreg	qacc_h_4			0x0306
+xtensa xtreg	qacc_l_0			0x0307
+xtensa xtreg	qacc_l_1			0x0308
+xtensa xtreg	qacc_l_2			0x0309
+xtensa xtreg	qacc_l_3			0x030a
+xtensa xtreg	qacc_l_4			0x030b
+xtensa xtreg	sar_byte			0x030d
+xtensa xtreg	fft_bit_width		0x030e
+xtensa xtreg	ua_state_0			0x030f
+xtensa xtreg	ua_state_1			0x0310
+xtensa xtreg	ua_state_2			0x0311
+xtensa xtreg	ua_state_3			0x0312
+xtensa xtreg	q0					0x1008
+xtensa xtreg	q1					0x1009
+xtensa xtreg	q2					0x100a
+xtensa xtreg	q3					0x100b
+xtensa xtreg	q4					0x100c
+xtensa xtreg	q5					0x100d
+xtensa xtreg	q6					0x100e
+xtensa xtreg	q7					0x100f
 xtensa xtreg	mmid				0x0259
 xtensa xtreg	ibreakenable		0x0260
 xtensa xtreg	memctl				0x0261
@@ -231,38 +226,38 @@ xtensa xtreg	misc0				0x02f4
 xtensa xtreg	misc1				0x02f5
 xtensa xtreg	misc2				0x02f6
 xtensa xtreg	misc3				0x02f7
-xtensa xtreg	pwrctl				0x2025
-xtensa xtreg	pwrstat				0x2026
-xtensa xtreg	eristat				0x2027
-xtensa xtreg	cs_itctrl			0x2028
-xtensa xtreg	cs_claimset			0x2029
-xtensa xtreg	cs_claimclr			0x202a
-xtensa xtreg	cs_lockaccess		0x202b
-xtensa xtreg	cs_lockstatus		0x202c
-xtensa xtreg	cs_authstatus		0x202d
-xtensa xtreg	fault_info			0x203c
-xtensa xtreg	trax_id				0x203d
-xtensa xtreg	trax_control		0x203e
-xtensa xtreg	trax_status			0x203f
-xtensa xtreg	trax_data			0x2040
-xtensa xtreg	trax_address		0x2041
-xtensa xtreg	trax_pctrigger		0x2042
-xtensa xtreg	trax_pcmatch		0x2043
-xtensa xtreg	trax_delay			0x2044
-xtensa xtreg	trax_memstart		0x2045
-xtensa xtreg	trax_memend			0x2046
-xtensa xtreg	pmg					0x2054
-xtensa xtreg	pmpc				0x2055
-xtensa xtreg	pm0					0x2056
-xtensa xtreg	pm1					0x2057
-xtensa xtreg	pmctrl0				0x2058
-xtensa xtreg	pmctrl1				0x2059
-xtensa xtreg	pmstat0				0x205a
-xtensa xtreg	pmstat1				0x205b
-xtensa xtreg	ocdid				0x205c
-xtensa xtreg	ocd_dcrclr			0x205d
-xtensa xtreg	ocd_dcrset			0x205e
-xtensa xtreg	ocd_dsr				0x205f
+xtensa xtreg	pwrctl				0x2028
+xtensa xtreg	pwrstat				0x2029
+xtensa xtreg	eristat				0x202a
+xtensa xtreg	cs_itctrl			0x202b
+xtensa xtreg	cs_claimset			0x202c
+xtensa xtreg	cs_claimclr			0x202d
+xtensa xtreg	cs_lockaccess		0x202e
+xtensa xtreg	cs_lockstatus		0x202f
+xtensa xtreg	cs_authstatus		0x2030
+xtensa xtreg	fault_info			0x203f
+xtensa xtreg	trax_id				0x2040
+xtensa xtreg	trax_control		0x2041
+xtensa xtreg	trax_status			0x2042
+xtensa xtreg	trax_data			0x2043
+xtensa xtreg	trax_address		0x2044
+xtensa xtreg	trax_pctrigger		0x2045
+xtensa xtreg	trax_pcmatch		0x2046
+xtensa xtreg	trax_delay			0x2047
+xtensa xtreg	trax_memstart		0x2048
+xtensa xtreg	trax_memend			0x2049
+xtensa xtreg	pmg					0x2057
+xtensa xtreg	pmpc				0x2058
+xtensa xtreg	pm0					0x2059
+xtensa xtreg	pm1					0x205a
+xtensa xtreg	pmctrl0				0x205b
+xtensa xtreg	pmctrl1				0x205c
+xtensa xtreg	pmstat0				0x205d
+xtensa xtreg	pmstat1				0x205e
+xtensa xtreg	ocdid				0x205f
+xtensa xtreg	ocd_dcrclr			0x2060
+xtensa xtreg	ocd_dcrset			0x2061
+xtensa xtreg	ocd_dsr				0x2062
 xtensa xtreg	a0					0x0000
 xtensa xtreg	a1					0x0001
 xtensa xtreg	a2					0x0002
@@ -279,19 +274,3 @@ xtensa xtreg	a12					0x000c
 xtensa xtreg	a13					0x000d
 xtensa xtreg	a14					0x000e
 xtensa xtreg	a15					0x000f
-xtensa xtreg	b0					0x0010
-xtensa xtreg	b1					0x0011
-xtensa xtreg	b2					0x0012
-xtensa xtreg	b3					0x0013
-xtensa xtreg	b4					0x0014
-xtensa xtreg	b5					0x0015
-xtensa xtreg	b6					0x0016
-xtensa xtreg	b7					0x0017
-xtensa xtreg	b8					0x0018
-xtensa xtreg	b9					0x0019
-xtensa xtreg	b10					0x001a
-xtensa xtreg	b11					0x001b
-xtensa xtreg	b12					0x001c
-xtensa xtreg	b13					0x001d
-xtensa xtreg	b14					0x001e
-xtensa xtreg	b15					0x001f

tools/scripts/checkpatch.pl

@@ -995,8 +995,10 @@ sub read_words {
 
 # OpenOCD specific: Begin: Load list of allowed CamelCase symbols
 if (show_type("CAMELCASE")) {
-	my $allowed_camelcase_file = "$root/tools/scripts/camelcase.txt";
-	if (open(my $words, '<', $allowed_camelcase_file)) {
+	my $allowed_camelcase_file = "tools/scripts/camelcase.txt";
+	if (!$root) {
+		warn "Ignore list of allowed camelcase symbols.\n";
+	} elsif (open(my $words, '<', "$root/$allowed_camelcase_file")) {
 		while (<$words>) {
 			 my $line = $_;
 
@@ -1012,9 +1014,9 @@ if (show_type("CAMELCASE")) {
 
 			$camelcase{$line} = 1;
 		}
-		close($allowed_camelcase_file);
+		close("$root/$allowed_camelcase_file");
 	} else {
-		warn "No camelcase symbols to ignore - file '$allowed_camelcase_file': $!\n";
+		warn "Failed opening file '$root/$allowed_camelcase_file': $!\n";
 	}
 }
 # OpenOCD specific: End