The openocd-0.7.0-rc2 release candidate.

Change-Id: I0a3576dd098d73437547b619c726cacd8f1dba64
Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>

NEWS

@@ -4,16 +4,30 @@ repository history for details about what changed, including
 bugfixes and other issues not mentioned here.
 
 JTAG Layer:
+	New TI ICDI adapter support.
+	Support Latest OSBDM firmware.
+	Improved MIPS EJTAG Support.
 
 Boundary Scan:
 
 Target Layer:
+	New ARMv7R and Cortex-R4 support.
+	Added ChibiOS/RT support.
 
 Flash Layer:
+	New NXP LPC1850 support.
+	New NXP LPC4300 support.
+	New NXP SPIFI support.
+	New Energy Micro EFM32 support.
+	New ST STM32W support.
+	New ST STM32f2 write protection and lock/unlock support.
+	Ability to override STM32 flash bank size.
 
 Board, Target, and Interface Configuration Scripts:
+	Support Freescale i.MX6 series targets.
 
 Documentation:
+	New MIPS debugging info.
 
 Build and Release:
 

configure.ac

@@ -1,5 +1,5 @@
 AC_PREREQ(2.60)
-AC_INIT([openocd], [0.7.0-rc1],
+AC_INIT([openocd], [0.7.0-rc2],
   [OpenOCD Mailing List <openocd-devel@lists.sourceforge.net>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 
@@ -961,7 +961,7 @@ if test $build_ft2232_ftd2xx = yes -o $build_presto_ftd2xx = yes -o $build_usb_b
       fi
     fi
     LDFLAGS="${LDFLAGS} ${FTD2XX_LDFLAGS}"
-    LIBS="${LIBS} ${FTD2XX_LIB}"
+    LIBS="${FTD2XX_LIB} ${LIBS}"
     AC_MSG_RESULT([${FTD2XX_LDFLAGS} ${FTD2XX_LIB}])
   else
     AC_CHECK_HEADER([ftd2xx.h],[],[

doc/openocd.texi

@@ -161,9 +161,9 @@ debugged via the GDB protocol.
 
 @b{Flash Programing:} Flash writing is supported for external CFI
 compatible NOR flashes (Intel and AMD/Spansion command set) and several
-internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3,
-STM32x and EFM32). Preliminary support for various NAND flash controllers
-(LPC3180, Orion, S3C24xx, more) controller is included.
+internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
+STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
+controllers (LPC3180, Orion, S3C24xx, more) controller is included.
 
 @section OpenOCD Web Site
 
@@ -986,7 +986,7 @@ that the @code{reset-init} event handler does.
 Likewise, the @command{arm9 vector_catch} command (or
 @cindex vector_catch
 its siblings @command{xscale vector_catch}
-and @command{cortex_m3 vector_catch}) can be a timesaver
+and @command{cortex_m vector_catch}) can be a timesaver
 during some debug sessions, but don't make everyone use that either.
 Keep those kinds of debugging aids in your user config file,
 along with messaging and tracing setup.
@@ -1878,14 +1878,14 @@ After setting targets, you can define a list of targets working in SMP.
 @example
 set _TARGETNAME_1 $_CHIPNAME.cpu1
 set _TARGETNAME_2 $_CHIPNAME.cpu2
-target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
 -coreid 0 -dbgbase $_DAP_DBG1
-target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
 -coreid 1 -dbgbase $_DAP_DBG2
 #define 2 targets working in smp.
 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
 @end example
-In the above example on cortex_a8, 2 cpus are working in SMP.
+In the above example on cortex_a, 2 cpus are working in SMP.
 In SMP only one GDB instance is created and :
 @itemize @bullet
 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
@@ -1896,32 +1896,32 @@ In SMP only one GDB instance is created and :
 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
 @end itemize
 
-The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
+The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
 command have been implemented.
 @itemize @bullet
-@item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
-@item cortex_a8 smp_off : disable SMP mode, the current target is the one
+@item cortex_a smp_on : enable SMP mode, behaviour is as described above.
+@item cortex_a smp_off : disable SMP mode, the current target is the one
 displayed in the GDB session, only this target is now controlled by GDB
 session. This behaviour is useful during system boot up.
-@item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
+@item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
 following example.
 @end itemize
 
 @example
->cortex_a8 smp_gdb
+>cortex_a smp_gdb
 gdb coreid  0 -> -1
 #0 : coreid 0 is displayed to GDB ,
 #-> -1 : next resume triggers a real resume
-> cortex_a8 smp_gdb 1
+> cortex_a smp_gdb 1
 gdb coreid  0 -> 1
 #0 :coreid 0 is displayed to GDB ,
 #->1  : next resume displays coreid 1 to GDB
 > resume
-> cortex_a8 smp_gdb
+> cortex_a smp_gdb
 gdb coreid  1 -> 1
 #1 :coreid 1 is displayed to GDB ,
 #->1 : next resume displays coreid 1 to GDB
-> cortex_a8 smp_gdb -1
+> cortex_a smp_gdb -1
 gdb coreid  1 -> -1
 #1 :coreid 1 is displayed to GDB,
 #->-1 : next resume triggers a real resume
@@ -1948,7 +1948,7 @@ don't want to reset all targets at once.
 Such a handler might write to chip registers to force a reset,
 use a JRC to do that (preferable -- the target may be wedged!),
 or force a watchdog timer to trigger.
-(For Cortex-M3 targets, this is not necessary. The target
+(For Cortex-M targets, this is not necessary.  The target
 driver knows how to use trigger an NVIC reset when SRST is
 not available.)
 
@@ -3953,7 +3953,7 @@ look like with more than one:
     TargetName         Type       Endian TapName            State
 --  ------------------ ---------- ------ ------------------ ------------
  0* at91rm9200.cpu     arm920t    little at91rm9200.cpu     running
- 1  MyTarget           cortex_m3  little mychip.foo         tap-disabled
+ 1  MyTarget           cortex_m   little mychip.foo         tap-disabled
 @end verbatim
 
 One member of that list is the @dfn{current target}, which
@@ -4064,8 +4064,8 @@ At this writing, the supported CPU types and variants are:
 @item @code{arm9tdmi} -- this is an ARMv4 core
 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
 (Support for this is preliminary and incomplete.)
-@item @code{cortex_a8} -- this is an ARMv7 core with an MMU
-@item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
+@item @code{cortex_a} -- this is an ARMv7 core with an MMU
+@item @code{cortex_m} -- this is an ARMv7 core, supporting only the
 compact Thumb2 instruction set.
 @item @code{dragonite} -- resembles arm966e
 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
@@ -4119,7 +4119,7 @@ to be much more board-specific.
 The key steps you use might look something like this
 
 @example
-target create MyTarget cortex_m3 -chain-position mychip.cpu
+target create MyTarget cortex_m -chain-position mychip.cpu
 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
 $MyTarget configure -event reset-init @{ myboard_reinit @}
@@ -5014,8 +5014,9 @@ supported.}
 @end deffn
 
 @deffn {Flash Driver} lpc2000
-Most members of the LPC1700 and LPC2000 microcontroller families from NXP
-include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
+Most members of the LPC1700, LPC1800, LPC2000 and LPC4300 microcontroller
+families from NXP include internal flash and use Cortex-M3 (LPC1700, LPC1800),
+Cortex-M4 (LPC4300) or ARM7TDMI (LPC2000) cores.
 
 @quotation Note
 There are LPC2000 devices which are not supported by the @var{lpc2000}
@@ -5031,7 +5032,9 @@ which must appear in the following order:
 @item @var{variant} ... required, may be
 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
-or @option{lpc1700} (LPC175x and LPC176x)
+@option{lpc1700} (LPC175x and LPC176x)
+or @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
+LPC43x[2357])
 @item @var{clock_kHz} ... the frequency, in kiloHertz,
 at which the core is running
 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
@@ -7297,7 +7300,7 @@ cores @emph{except the ARM1176} use the same six bits.
 @cindex Debug Access Port
 @cindex DAP
 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
-included on Cortex-M3 and Cortex-A8 systems.
+included on Cortex-M and Cortex-A systems.
 They are available in addition to other core-specific commands that may be available.
 
 @deffn Command {dap apid} [num]
@@ -7330,10 +7333,10 @@ fix CSW_SPROT from register AP_REG_CSW on selected dap.
 Defaulting to 0.
 @end deffn
 
-@subsection Cortex-M3 specific commands
-@cindex Cortex-M3
+@subsection Cortex-M specific commands
+@cindex Cortex-M
 
-@deffn Command {cortex_m3 maskisr} (@option{auto}|@option{on}|@option{off})
+@deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
 Control masking (disabling) interrupts during target step/resume.
 
 The @option{auto} option handles interrupts during stepping a way they get
@@ -7350,7 +7353,7 @@ with interrupts enabled, i.e. the same way the @option{off} option does.
 Default is @option{auto}.
 @end deffn
 
-@deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
+@deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
 @cindex vector_catch
 Vector Catch hardware provides dedicated breakpoints
 for certain hardware events.
@@ -7377,7 +7380,7 @@ must also be explicitly enabled.
 This finishes by listing the current vector catch configuration.
 @end deffn
 
-@deffn Command {cortex_m3 reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
+@deffn Command {cortex_m reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
 Control reset handling. The default @option{srst} is to use srst if fitted,
 otherwise fallback to @option{vectreset}.
 @itemize @minus
@@ -7385,7 +7388,7 @@ otherwise fallback to @option{vectreset}.
 @item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
 @item @option{vectreset} use NVIC VECTRESET to reset system.
 @end itemize
-Using @option{vectreset} is a safe option for all current Cortex-M3 cores.
+Using @option{vectreset} is a safe option for all current Cortex-M cores.
 This however has the disadvantage of only resetting the core, all peripherals
 are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
 the peripherals.
@@ -7404,7 +7407,7 @@ The most powerful mechanism is semihosting, but there is also
 a lighter weight mechanism using only the DCC channel.
 
 Currently @command{target_request debugmsgs}
-is supported only for @option{arm7_9} and @option{cortex_m3} cores.
+is supported only for @option{arm7_9} and @option{cortex_m} cores.
 These messages are received as part of target polling, so
 you need to have @command{poll on} active to receive them.
 They are intrusive in that they will affect program execution
@@ -7910,10 +7913,10 @@ and an RTOS until he told GDB to disable the IRQs while stepping:
 
 @example
 define hook-step
-mon cortex_m3 maskisr on
+mon cortex_m maskisr on
 end
 define hookpost-step
-mon cortex_m3 maskisr off
+mon cortex_m maskisr off
 end
 @end example
 

src/flash/nor/kinetis.c

@@ -365,23 +365,27 @@ static int kinetis_write(struct flash_bank *bank, uint8_t *buffer,
 
 	/* program section command */
 	if (fallback == 0) {
-		unsigned prog_section_bytes = kinfo->sector_size >> 8;
-		for (i = 0; i < count; i += kinfo->sector_size) {
-			/*
-			 * The largest possible Kinetis "section" is
-			 * 16 bytes.  A full Kinetis sector is always
-			 * 256 "section"s.
-			 */
+		/*
+		 * Kinetis uses different terms for the granularity of
+		 * sector writes, e.g. "phrase" or "128 bits".  We use
+		 * the generic term "chunk". The largest possible
+		 * Kinetis "chunk" is 16 bytes (128 bits).
+		 */
+		unsigned prog_section_chunk_bytes = kinfo->sector_size >> 8;
+		/* assume the NVM sector size is half the FlexRAM size */
+		unsigned prog_size_bytes = MIN(kinfo->sector_size,
+					       kinetis_flash_params[kinfo->granularity].nvm_sector_size_bytes);
+		for (i = 0; i < count; i += prog_size_bytes) {
 			uint8_t residual_buffer[16];
 			uint8_t ftfx_fstat;
-			uint32_t section_count = 256;
+			uint32_t section_count = prog_size_bytes / prog_section_chunk_bytes;
 			uint32_t residual_wc = 0;
 
 			/*
 			 * Assume the word count covers an entire
 			 * sector.
 			 */
-			wc = kinfo->sector_size / 4;
+			wc = prog_size_bytes / 4;
 
 			/*
 			 * If bytes to be programmed are less than the
@@ -390,21 +394,21 @@ static int kinetis_write(struct flash_bank *bank, uint8_t *buffer,
 			 * residual buffer so that a full "section"
 			 * may always be programmed.
 			 */
-			if ((count - i) < kinfo->sector_size) {
+			if ((count - i) < prog_size_bytes) {
 				/* number of bytes to program beyond full section */
-				unsigned residual_bc = (count-i) % prog_section_bytes;
+				unsigned residual_bc = (count-i) % prog_section_chunk_bytes;
 
 				/* number of complete words to copy directly from buffer */
 				wc = (count - i) / 4;
 
 				/* number of total sections to write, including residual */
-				section_count = DIV_ROUND_UP((count-i), prog_section_bytes);
+				section_count = DIV_ROUND_UP((count-i), prog_section_chunk_bytes);
 
 				/* any residual bytes delivers a whole residual section */
-				residual_wc = (residual_bc ? prog_section_bytes : 0)/4;
+				residual_wc = (residual_bc ? prog_section_chunk_bytes : 0)/4;
 
 				/* clear residual buffer then populate residual bytes */
-				(void) memset(residual_buffer, 0xff, prog_section_bytes);
+				(void) memset(residual_buffer, 0xff, prog_section_chunk_bytes);
 				(void) memcpy(residual_buffer, &buffer[i+4*wc], residual_bc);
 			}
 
@@ -770,7 +774,7 @@ static int kinetis_blank_check(struct flash_bank *bank)
 			for (i = 0; i < bank->num_sectors; i++) {
 				/* normal margin */
 				result = kinetis_ftfx_command(bank, FTFx_CMD_SECTSTAT, bank->base + bank->sectors[i].offset,
-						0, 0, 0, 1,  0, 0, 0, 0, &ftfx_fstat);
+						1, 0, 0, 0,  0, 0, 0, 0, &ftfx_fstat);
 
 				if (result == ERROR_OK) {
 					bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);

src/jtag/drivers/ft2232.c

@@ -3141,9 +3141,8 @@ static void flossjtag_blink(void)
 static int ft2232_quit(void)
 {
 #if BUILD_FT2232_FTD2XX == 1
-	FT_STATUS status;
 
-	status = FT_Close(ftdih);
+	FT_Close(ftdih);
 #elif BUILD_FT2232_LIBFTDI == 1
 	ftdi_usb_close(&ftdic);
 

src/rtos/ChibiOS.c

@@ -94,7 +94,7 @@ struct ChibiOS_params {
 
 struct ChibiOS_params ChibiOS_params_list[] = {
 	{
-	"cortex_m3",							/* target_name */
+	"cortex_m",							/* target_name */
 	0,
 	NULL,									/* stacking_info */
 	},

src/rtos/FreeRTOS.c

@@ -50,7 +50,7 @@ struct FreeRTOS_params {
 
 const struct FreeRTOS_params FreeRTOS_params_list[] = {
 	{
-	"cortex_m3",			/* target_name */
+	"cortex_m",			/* target_name */
 	4,						/* thread_count_width; */
 	4,						/* pointer_width; */
 	16,						/* list_next_offset; */

src/rtos/ThreadX.c

@@ -73,7 +73,7 @@ struct ThreadX_params {
 
 const struct ThreadX_params ThreadX_params_list[] = {
 	{
-	"cortex_m3",				/* target_name */
+	"cortex_m",				/* target_name */
 	4,							/* pointer_width; */
 	8,							/* thread_stack_offset; */
 	40,							/* thread_name_offset; */

src/rtos/eCos.c

@@ -64,7 +64,7 @@ struct eCos_params {
 
 const struct eCos_params eCos_params_list[] = {
 	{
-	"cortex_m3",			/* target_name */
+	"cortex_m",			/* target_name */
 	4,						/* pointer_width; */
 	0x0c,					/* thread_stack_offset; */
 	0x9c,					/* thread_name_offset; */

src/server/gdb_server.c

@@ -1259,7 +1259,7 @@ static int gdb_write_memory_packet(struct connection *connection,
 
 	LOG_DEBUG("addr: 0x%8.8" PRIx32 ", len: 0x%8.8" PRIx32 "", addr, len);
 
-	if (unhexify((char *)buffer, separator + 2, len) != (int)len)
+	if (unhexify((char *)buffer, separator, len) != (int)len)
 		LOG_ERROR("unable to decode memory packet");
 
 	retval = target_write_buffer(target, addr, len, buffer);

src/target/arm11.c

@@ -1094,6 +1094,7 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
 	if (!arm11)
 		return ERROR_FAIL;
 
+	arm11->arm.core_type = ARM_MODE_ANY;
 	arm_init_arch_info(target, &arm11->arm);
 
 	arm11->jtag_info.tap = target->tap;

src/target/arm7_9_common.c

@@ -2806,6 +2806,7 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
 	arm7_9->dcc_downloads = false;
 
 	arm->arch_info = arm7_9;
+	arm->core_type = ARM_MODE_ANY;
 	arm->read_core_reg = arm7_9_read_core_reg;
 	arm->write_core_reg = arm7_9_write_core_reg;
 	arm->full_context = arm7_9_full_context;

src/target/cortex_a.c

@@ -2746,9 +2746,9 @@ static const struct command_registration cortex_a8_command_handlers[] = {
 		.chain = armv7a_command_handlers,
 	},
 	{
-		.name = "cortex_a8",
+		.name = "cortex_a",
 		.mode = COMMAND_ANY,
-		.help = "Cortex-A8 command group",
+		.help = "Cortex-A command group",
 		.usage = "",
 		.chain = cortex_a8_exec_command_handlers,
 	},

src/target/cortex_m.c

@@ -1796,6 +1796,9 @@ fail1:
 		for (j = 0; j < 3; j++, reg++)
 			cortex_m3_dwt_addreg(target, cache->reg_list + reg,
 				dwt_comp + 3 * i + j);
+
+		/* make sure we clear any watchpoints enabled on the target */
+		target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
 	}
 
 	*register_get_last_cache_p(&target->reg_cache) = cache;
@@ -1887,6 +1890,9 @@ int cortex_m3_examine(struct target *target)
 			cortex_m3->fp_comparator_list[i].type =
 				(i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
 			cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
+
+			/* make sure we clear any breakpoints enabled on the target */
+			target_write_u32(target, cortex_m3->fp_comparator_list[i].fpcr_address, 0);
 		}
 		LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
 			fpcr,
@@ -2250,9 +2256,9 @@ static const struct command_registration cortex_m3_command_handlers[] = {
 		.chain = armv7m_command_handlers,
 	},
 	{
-		.name = "cortex_m3",
+		.name = "cortex_m",
 		.mode = COMMAND_EXEC,
-		.help = "Cortex-M3 command group",
+		.help = "Cortex-M command group",
 		.usage = "",
 		.chain = cortex_m3_exec_command_handlers,
 	},
@@ -2260,7 +2266,8 @@ static const struct command_registration cortex_m3_command_handlers[] = {
 };
 
 struct target_type cortexm3_target = {
-	.name = "cortex_m3",
+	.name = "cortex_m",
+	.deprecated_name = "cortex_m3",
 
 	.poll = cortex_m3_poll,
 	.arch_state = armv7m_arch_state,

src/target/startup.tcl

@@ -167,3 +167,14 @@ proc init_targets {} {
 # Additionally board config scripts can define a procedure init_board that will be executed after init and init_targets
 proc init_board {} {
 }
+
+# deprecated target name cmds
+proc cortex_m3 args {
+	echo "DEPRECATED! use 'cortex_m' not 'cortex_m3'"
+	eval cortex_m $args
+}
+
+proc cortex_a8 args {
+	echo "DEPRECATED! use 'cortex_a' not 'cortex_a8'"
+	eval cortex_a $args
+}

src/target/xscale.c

@@ -2997,6 +2997,7 @@ static int xscale_init_arch_info(struct target *target,
 
 	/* prepare ARMv4/5 specific information */
 	arm->arch_info = xscale;
+	arm->core_type = ARM_MODE_ANY;
 	arm->read_core_reg = xscale_read_core_reg;
 	arm->write_core_reg = xscale_write_core_reg;
 	arm->full_context = xscale_full_context;

tcl/board/icnova_imx53_sodimm.cfg

@@ -19,7 +19,7 @@ adapter_khz 3000
 
 $_TARGETNAME configure -event "reset-assert" {
 	echo "Reseting ...."
-	#cortex_a8 dbginit
+	#cortex_a dbginit
 }
 
 $_TARGETNAME configure -event reset-init { sodimm_init }

tcl/board/imx53loco.cfg

@@ -20,7 +20,7 @@ adapter_khz 3000
 
 $_TARGETNAME configure -event "reset-assert" {
 	echo "Reseting ...."
-	#cortex_a8 dbginit
+	#cortex_a dbginit
 }
 
 $_TARGETNAME configure -event reset-init { loco_init }

tcl/target/am335x.cfg

@@ -64,13 +64,13 @@ jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
 # Cortex A8 target
 #
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
 
 # SRAM: 64K at 0x4030.0000; use the first 16K
 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
 
 $_TARGETNAME configure -event gdb-attach {
-   cortex_a8 dbginit
+   cortex_a dbginit
    halt
 }
 

tcl/target/amdm37x.cfg

@@ -141,7 +141,7 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
 
 # Create the CPU target to be used with GDB:  Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
 
 # The DM37x has 64K of SRAM starting at address 0x4020_0000.  Allow the first
 # 16K to be used as a scratchpad for OpenOCD.
@@ -200,7 +200,7 @@ $_TARGETNAME configure -event gdb-attach {
 # reset sequence.
 proc amdm37x_dbginit {target} {
    # General Cortex A8 debug initialisation
-   cortex_a8 dbginit
+   cortex_a dbginit
 
    # Enable DBGEN signal.  This signal is described in the ARM v7 TRM, but
    # access to the signal appears to be implementation specific.  TI does not

tcl/target/at91sam3XXX.cfg

@@ -58,7 +58,7 @@ if { [info exists CPUTAPID] } {
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # 16K is plenty, the smallest chip has this much
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
@@ -69,4 +69,4 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/at91sam3nXX.cfg

@@ -18,12 +18,12 @@ if { [info exists CPUTAPID] } {
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian little -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq
 

tcl/target/at91sam4XXX.cfg

@@ -35,7 +35,7 @@ if { [info exists CPUTAPID] } {
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # 16K is plenty, the smallest chip has this much
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
@@ -46,4 +46,4 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/fm3.cfg

@@ -29,7 +29,7 @@ reset_config trst_only
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # MB9BF506 has 64kB of SRAM on its main system bus 
 $_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
@@ -44,4 +44,4 @@ adapter_khz 500
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/imx51.cfg

@@ -31,7 +31,7 @@ jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
 
 # GDB target: Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
 
 # some TCK tycles are required to activate the DEBUG power domain
 jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
@@ -41,7 +41,7 @@ jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
 
 proc imx51_dbginit {target} {
      # General Cortex A8 debug initialisation
-     cortex_a8 dbginit
+     cortex_a dbginit
 }
 
 # Slow speed to be sure it will work

tcl/target/imx53.cfg

@@ -31,7 +31,7 @@ jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
 
 # GDB target: Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
 
 # some TCK tycles are required to activate the DEBUG power domain
 jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
@@ -41,7 +41,7 @@ jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
 
 proc imx53_dbginit {target} {
      # General Cortex A8 debug initialisation
-     cortex_a8 dbginit
+     cortex_a dbginit
 }
 
 # Slow speed to be sure it will work

tcl/target/k40.cfg

@@ -29,11 +29,11 @@ set _TARGETNAME $_CHIPNAME.cpu
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
 
 $_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
 $_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/k60.cfg

@@ -29,11 +29,11 @@ set _TARGETNAME $_CHIPNAME.cpu
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
 
 $_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
 $_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/lpc1788.cfg

@@ -17,4 +17,4 @@ set CCLK 12000
 source [find target/lpc17xx.cfg];
 
 # if srst is not fitted, use SYSRESETREQ to perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/lpc17xx.cfg

@@ -57,7 +57,7 @@ jtag_ntrst_delay 200
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
 
 # The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
@@ -94,4 +94,4 @@ $_TARGETNAME configure -event reset-init {
 
 # if srst is not fitted use VECTRESET to
 # perform a soft reset - SYSRESETREQ is not supported
-cortex_m3 reset_config vectreset
+cortex_m reset_config vectreset

tcl/target/lpc1850.cfg

@@ -24,8 +24,8 @@ if { [info exists M3_JTAG_TAPID] } {
 jtag newtap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
 
 set _TARGETNAME $_CHIPNAME.m3
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/lpc4350.cfg

@@ -40,12 +40,12 @@ jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
 jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
 				-expected-id $_M0_JTAG_TAPID
 
-target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4
-target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0
+target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
 
 # on this CPU we should use VECTRESET to perform a soft reset and
 # manually reset the periphery
 # SRST or SYSRESETREQ disable the debug interface for the time of
 # the reset and will not fit our requirements for a consistent debug
 # session
-cortex_m3 reset_config vectreset
+cortex_m reset_config vectreset

tcl/target/omap3530.cfg

@@ -36,7 +36,7 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
 
 # GDB target: Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
 
 # SRAM: 64K at 0x4020.0000; use the first 16K
 $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
@@ -54,7 +54,7 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
 
 proc omap3_dbginit {target} {
      # General Cortex A8 debug initialisation
-     cortex_a8 dbginit
+     cortex_a dbginit
      # Enable DBGU signal for OMAP353x
      $target mww phys 0x5401d030 0x00002000
 }

tcl/target/omap4430.cfg

@@ -94,7 +94,7 @@ set _coreid 0
 set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
 echo "Using dbgbase = [format 0x%x $_dbgbase]"
  
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
   -coreid 0 -dbgbase $_dbgbase
 
 # SRAM: 56KiB at 0x4030.0000
@@ -104,8 +104,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
 #
 # M3 targets, separate TAP/DAP for each core
 #
-target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap
-target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap
+target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
 
 
 # Once the JRC is up, enable our TAPs

tcl/target/omap4460.cfg

@@ -94,7 +94,7 @@ set _coreid 0
 set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
 echo "Using dbgbase = [format 0x%x $_dbgbase]"
 
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
   -coreid 0 -dbgbase $_dbgbase
 
 # SRAM: 56KiB at 0x4030.0000
@@ -104,8 +104,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
 #
 # M3 targets, separate TAP/DAP for each core
 #
-target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap
-target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap
+target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
 
 
 # Once the JRC is up, enable our TAPs

tcl/target/stellaris.cfg

@@ -52,7 +52,7 @@ if { [info exists WORKAREASIZE] } {
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
 
 # 8K working area at base of ram, not backed up
 #
@@ -157,11 +157,11 @@ $_TARGETNAME configure -event reset-start {
 	if {$device_class == 0 || $device_class == 1 ||
 		$device_class == 3 || $device_class == 5} {
 		# Sandstorm, Fury, DustDevil and Blizzard are able to use NVIC SYSRESETREQ
-		cortex_m3 reset_config sysresetreq
+		cortex_m reset_config sysresetreq
 	} else {
 		# Tempest and Firestorm default to using NVIC VECTRESET
 		# peripherals will need reseting manually, see proc reset_peripherals
-		cortex_m3 reset_config vectreset
+		cortex_m reset_config vectreset
 
 		# reset peripherals, based on code in
 		# http://www.ti.com/lit/er/spmz573a/spmz573a.pdf

tcl/target/stm32f1x.cfg

@@ -68,7 +68,7 @@ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
 	-expected-id $_BSTAPID8 -expected-id $_BSTAPID9
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -78,4 +78,4 @@ flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/stm32f2x.cfg

@@ -52,7 +52,7 @@ if { [info exists BSTAPID] } {
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -61,4 +61,4 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/stm32f3x.cfg

@@ -52,7 +52,7 @@ if { [info exists BSTAPID] } {
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -61,4 +61,4 @@ flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/stm32f4x.cfg

@@ -51,7 +51,7 @@ if { [info exists BSTAPID] } {
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -60,4 +60,4 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/stm32l.cfg

@@ -48,7 +48,7 @@ if { [info exists BSTAPID] } {
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -59,7 +59,7 @@ flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq
 
 proc stm32l_enable_HSI {} {
 	# Enable HSI as clock source

tcl/target/u8500.cfg

@@ -19,12 +19,12 @@ proc ocd_gdb_restart {target_id} {
 	global _SMP
     targets $_TARGETNAME_1
 	if { [expr ($_SMP == 1)] } {
-	cortex_a8 smp_off
+	cortex_a smp_off
 	}
 	rst_run
 	halt
 	if { [expr ($_SMP == 1)]} {
-	cortex_a8 smp_on
+	cortex_a smp_on
 	}
 }
 
@@ -202,7 +202,7 @@ if { [info exists DAP_DBG2] } {
 	set _DAP_DBG2 0x801AA000 
 }
 
-target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
+target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
 
 $_TARGETNAME_1 configure -event gdb-attach {
 	halt
@@ -217,7 +217,7 @@ global _TARGETNAME_2
 set _TARGETNAME_2 $TARGETNAME_2
 }
 
-target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
+target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
 
 $_TARGETNAME_2 configure -event gdb-attach {
 	halt