The openocd-0.7.0 release.

Change-Id: I08157f47ac056e6d2089119dd2d6cbab11b521e8
Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>

NEWS

@@ -4,16 +4,30 @@ repository history for details about what changed, including
 bugfixes and other issues not mentioned here.
 
 JTAG Layer:
+	New TI ICDI adapter support.
+	Support Latest OSBDM firmware.
+	Improved MIPS EJTAG Support.
 
 Boundary Scan:
 
 Target Layer:
+	New ARMv7R and Cortex-R4 support.
+	Added ChibiOS/RT support.
 
 Flash Layer:
+	New NXP LPC1850 support.
+	New NXP LPC4300 support.
+	New NXP SPIFI support.
+	New Energy Micro EFM32 support.
+	New ST STM32W support.
+	New ST STM32f2 write protection and lock/unlock support.
+	Ability to override STM32 flash bank size.
 
 Board, Target, and Interface Configuration Scripts:
+	Support Freescale i.MX6 series targets.
 
 Documentation:
+	New MIPS debugging info.
 
 Build and Release:
 

configure.ac

@@ -1,5 +1,5 @@
 AC_PREREQ(2.60)
-AC_INIT([openocd], [0.7.0-rc1],
+AC_INIT([openocd], [0.7.0],
   [OpenOCD Mailing List <openocd-devel@lists.sourceforge.net>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 
@@ -961,7 +961,7 @@ if test $build_ft2232_ftd2xx = yes -o $build_presto_ftd2xx = yes -o $build_usb_b
       fi
     fi
     LDFLAGS="${LDFLAGS} ${FTD2XX_LDFLAGS}"
-    LIBS="${LIBS} ${FTD2XX_LIB}"
+    LIBS="${FTD2XX_LIB} ${LIBS}"
     AC_MSG_RESULT([${FTD2XX_LDFLAGS} ${FTD2XX_LIB}])
   else
     AC_CHECK_HEADER([ftd2xx.h],[],[

doc/manual/release.txt

@@ -111,7 +111,7 @@ configure.ac script of a local copy of the source tree, giving
 a version label like <em>0.3.0-foo</em>:
 
 @code
-tools/release/version.sh version tag add foo
+tools/release/version.sh tag add foo
 @endcode
 
 This command will modify the configure.ac script in your working copy
@@ -125,7 +125,7 @@ each time a derived package is released, incrementing the tag's
 version to facilitate tracking the changes you have distributed.
 
 @code
-tools/release/version.sh version bump tag foo
+tools/release/version.sh bump tag foo
 @endcode
 
 Of course, any patches in your branches must be provided to

doc/openocd.texi

@@ -161,9 +161,9 @@ debugged via the GDB protocol.
 
 @b{Flash Programing:} Flash writing is supported for external CFI
 compatible NOR flashes (Intel and AMD/Spansion command set) and several
-internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3,
+internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
-STM32x and EFM32). Preliminary support for various NAND flash controllers
+STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
-(LPC3180, Orion, S3C24xx, more) controller is included.
+controllers (LPC3180, Orion, S3C24xx, more) controller is included.
 
 @section OpenOCD Web Site
 
@@ -336,8 +336,10 @@ on a chip from ``Future Technology Devices International'' (FTDI)
 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
 See: @url{http://www.ftdichip.com} for more information.
 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
-chips are starting to become available in JTAG adapters. (Adapters
+chips are starting to become available in JTAG adapters. Around 2012 a new
-using those high speed FT2232H chips may support adaptive clocking.)
+variant appeared - FT232H - this is a single-channel version of FT2232H.
+(Adapters using those high speed FT2232H or FT232H chips may support adaptive
+clocking.)
 
 The FT2232 chips are flexible enough to support some other
 transport options, such as SWD or the SPI variants used to
@@ -394,6 +396,8 @@ to be available anymore as of April 2012.
 @item @b{opendous}
 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
 (OpenHardware).
+@item @b{JTAG-lock-pick Tiny 2}
+@* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
 @end itemize
 
 @section USB-JTAG / Altera USB-Blaster compatibles
@@ -986,7 +990,7 @@ that the @code{reset-init} event handler does.
 Likewise, the @command{arm9 vector_catch} command (or
 @cindex vector_catch
 its siblings @command{xscale vector_catch}
-and @command{cortex_m3 vector_catch}) can be a timesaver
+and @command{cortex_m vector_catch}) can be a timesaver
 during some debug sessions, but don't make everyone use that either.
 Keep those kinds of debugging aids in your user config file,
 along with messaging and tracing setup.
@@ -1257,31 +1261,52 @@ Use them as-is where you can; or as models for new files.
 These are for debug adapters.
 Files that configure JTAG adapters go here.
 @example
-$ ls interface
+$ ls interface -R
-altera-usb-blaster.cfg    hilscher_nxhx50_etm.cfg    openrd.cfg
+interface/:
-arm-jtag-ew.cfg           hilscher_nxhx50_re.cfg     osbdm.cfg
+altera-usb-blaster.cfg    hilscher_nxhx50_re.cfg     openocd-usb-hs.cfg
-arm-usb-ocd.cfg           hitex_str9-comstick.cfg    parport.cfg
+arm-jtag-ew.cfg           hitex_str9-comstick.cfg    openrd.cfg
-at91rm9200.cfg            icebear.cfg                parport_dlc5.cfg
+at91rm9200.cfg            icebear.cfg                osbdm.cfg
-axm0432.cfg               jlink.cfg                  redbee-econotag.cfg
+axm0432.cfg               jlink.cfg                  parport.cfg
-busblaster.cfg            jtagkey2.cfg               redbee-usb.cfg
+busblaster.cfg            jtagkey2.cfg               parport_dlc5.cfg
-buspirate.cfg             jtagkey2p.cfg              rlink.cfg
+buspirate.cfg             jtagkey2p.cfg              redbee-econotag.cfg
-calao-usb-a9260-c01.cfg   jtagkey.cfg                sheevaplug.cfg
+calao-usb-a9260-c01.cfg   jtagkey.cfg                redbee-usb.cfg
-calao-usb-a9260-c02.cfg   jtagkey-tiny.cfg           signalyzer.cfg
+calao-usb-a9260-c02.cfg   jtagkey-tiny.cfg           rlink.cfg
-calao-usb-a9260.cfg       kt-link.cfg                signalyzer-h2.cfg
+calao-usb-a9260.cfg       jtag-lock-pick_tiny_2.cfg  sheevaplug.cfg
-chameleon.cfg             lisa-l.cfg                 signalyzer-h4.cfg
+chameleon.cfg             kt-link.cfg                signalyzer.cfg
-cortino.cfg               luminary.cfg               signalyzer-lite.cfg
+cortino.cfg               lisa-l.cfg                 signalyzer-h2.cfg
-digilent-hs1.cfg          luminary-icdi.cfg          stlink-v1.cfg
+digilent-hs1.cfg          luminary.cfg               signalyzer-h4.cfg
-dlp-usb1232h.cfg          luminary-lm3s811.cfg       stlink-v2.cfg
+dlp-usb1232h.cfg          luminary-icdi.cfg          signalyzer-lite.cfg
-dummy.cfg                 minimodule.cfg             stm32-stick.cfg
+dummy.cfg                 luminary-lm3s811.cfg       stlink-v1.cfg
-estick.cfg                neodb.cfg                  turtelizer2.cfg
+estick.cfg                minimodule.cfg             stlink-v2.cfg
-flashlink.cfg             ngxtech.cfg                ulink.cfg
+flashlink.cfg             neodb.cfg                  stm32-stick.cfg
-flossjtag.cfg             olimex-arm-usb-ocd.cfg     usb-jtag.cfg
+flossjtag.cfg             ngxtech.cfg                sysfsgpio-raspberrypi.cfg
-flossjtag-noeeprom.cfg    olimex-arm-usb-ocd-h.cfg   usbprog.cfg
+flossjtag-noeeprom.cfg    olimex-arm-usb-ocd.cfg     ti-icdi.cfg
-flyswatter2.cfg           olimex-arm-usb-tiny-h.cfg  vpaclink.cfg
+flyswatter2.cfg           olimex-arm-usb-ocd-h.cfg   turtelizer2.cfg
-flyswatter.cfg            olimex-jtag-tiny.cfg       vsllink.cfg
+flyswatter.cfg            olimex-arm-usb-tiny-h.cfg  ulink.cfg
-hilscher_nxhx10_etm.cfg   oocdlink.cfg               xds100v2.cfg
+ftdi                      olimex-jtag-tiny.cfg       usb-jtag.cfg
-hilscher_nxhx500_etm.cfg  opendous.cfg
+hilscher_nxhx10_etm.cfg   oocdlink.cfg               usbprog.cfg
-hilscher_nxhx500_re.cfg   openocd-usb.cfg
+hilscher_nxhx500_etm.cfg  opendous.cfg               vpaclink.cfg
+hilscher_nxhx500_re.cfg   opendous_ftdi.cfg          vsllink.cfg
+hilscher_nxhx50_etm.cfg   openocd-usb.cfg            xds100v2.cfg
+
+interface/ftdi:
+axm0432.cfg               icebear.cfg                oocdlink.cfg
+calao-usb-a9260-c01.cfg   jtagkey2.cfg               opendous_ftdi.cfg
+calao-usb-a9260-c02.cfg   jtagkey2p.cfg              openocd-usb.cfg
+cortino.cfg               jtagkey.cfg                openocd-usb-hs.cfg
+dlp-usb1232h.cfg          jtag-lock-pick_tiny_2.cfg  openrd.cfg
+dp_busblaster.cfg         kt-link.cfg                redbee-econotag.cfg
+flossjtag.cfg             lisa-l.cfg                 redbee-usb.cfg
+flossjtag-noeeprom.cfg    luminary.cfg               sheevaplug.cfg
+flyswatter2.cfg           luminary-icdi.cfg          signalyzer.cfg
+flyswatter.cfg            luminary-lm3s811.cfg       signalyzer-lite.cfg
+hilscher_nxhx10_etm.cfg   minimodule.cfg             stm32-stick.cfg
+hilscher_nxhx500_etm.cfg  neodb.cfg                  turtelizer2-revB.cfg
+hilscher_nxhx500_re.cfg   ngxtech.cfg                turtelizer2-revC.cfg
+hilscher_nxhx50_etm.cfg   olimex-arm-usb-ocd.cfg     vpaclink.cfg
+hilscher_nxhx50_re.cfg    olimex-arm-usb-ocd-h.cfg   xds100v2.cfg
+hitex_lpc1768stick.cfg    olimex-arm-usb-tiny-h.cfg
+hitex_str9-comstick.cfg   olimex-jtag-tiny.cfg
 $
 @end example
 @item @file{board} ...
@@ -1297,72 +1322,77 @@ board file. Boards may also contain multiple targets: two CPUs; or
 a CPU and an FPGA.
 @example
 $ ls board
-actux3.cfg                        logicpd_imx27.cfg
+actux3.cfg                        lpc1850_spifi_generic.cfg
-am3517evm.cfg                     lubbock.cfg
+am3517evm.cfg                     lpc4350_spifi_generic.cfg
-arm_evaluator7t.cfg               mcb1700.cfg
+arm_evaluator7t.cfg               lubbock.cfg
-at91cap7a-stk-sdram.cfg           microchip_explorer16.cfg
+at91cap7a-stk-sdram.cfg           mcb1700.cfg
-at91eb40a.cfg                     mini2440.cfg
+at91eb40a.cfg                     microchip_explorer16.cfg
-at91rm9200-dk.cfg                 mini6410.cfg
+at91rm9200-dk.cfg                 mini2440.cfg
-at91rm9200-ek.cfg                 olimex_LPC2378STK.cfg
+at91rm9200-ek.cfg                 mini6410.cfg
-at91sam9261-ek.cfg                olimex_lpc_h2148.cfg
+at91sam9261-ek.cfg                netgear-dg834v3.cfg
-at91sam9263-ek.cfg                olimex_sam7_ex256.cfg
+at91sam9263-ek.cfg                olimex_LPC2378STK.cfg
-at91sam9g20-ek.cfg                olimex_sam9_l9260.cfg
+at91sam9g20-ek.cfg                olimex_lpc_h2148.cfg
-atmel_at91sam7s-ek.cfg            olimex_stm32_h103.cfg
+atmel_at91sam7s-ek.cfg            olimex_sam7_ex256.cfg
-atmel_at91sam9260-ek.cfg          olimex_stm32_h107.cfg
+atmel_at91sam9260-ek.cfg          olimex_sam9_l9260.cfg
-atmel_at91sam9rl-ek.cfg           olimex_stm32_p107.cfg
+atmel_at91sam9rl-ek.cfg           olimex_stm32_h103.cfg
-atmel_sam3n_ek.cfg                omap2420_h4.cfg
+atmel_sam3n_ek.cfg                olimex_stm32_h107.cfg
-atmel_sam3s_ek.cfg                open-bldc.cfg
+atmel_sam3s_ek.cfg                olimex_stm32_p107.cfg
-atmel_sam3u_ek.cfg                openrd.cfg
+atmel_sam3u_ek.cfg                omap2420_h4.cfg
-atmel_sam3x_ek.cfg                osk5912.cfg
+atmel_sam3x_ek.cfg                open-bldc.cfg
-atmel_sam4s_ek.cfg                phytec_lpc3250.cfg
+atmel_sam4s_ek.cfg                openrd.cfg
-balloon3-cpu.cfg                  pic-p32mx.cfg
+balloon3-cpu.cfg                  osk5912.cfg
-colibri.cfg                       propox_mmnet1001.cfg
+colibri.cfg                       phone_se_j100i.cfg
-crossbow_tech_imote2.cfg          pxa255_sst.cfg
+crossbow_tech_imote2.cfg          phytec_lpc3250.cfg
-csb337.cfg                        redbee.cfg
+csb337.cfg                        pic-p32mx.cfg
-csb732.cfg                        rsc-w910.cfg
+csb732.cfg                        propox_mmnet1001.cfg
-da850evm.cfg                      sheevaplug.cfg
+da850evm.cfg                      pxa255_sst.cfg
-digi_connectcore_wi-9c.cfg        smdk6410.cfg
+digi_connectcore_wi-9c.cfg        redbee.cfg
-diolan_lpc4350-db1.cfg            spear300evb.cfg
+diolan_lpc4350-db1.cfg            rsc-w910.cfg
-dm355evm.cfg                      spear300evb_mod.cfg
+dm355evm.cfg                      sheevaplug.cfg
-dm365evm.cfg                      spear310evb20.cfg
+dm365evm.cfg                      smdk6410.cfg
-dm6446evm.cfg                     spear310evb20_mod.cfg
+dm6446evm.cfg                     spear300evb.cfg
-efikamx.cfg                       spear320cpu.cfg
+efikamx.cfg                       spear300evb_mod.cfg
-eir.cfg                           spear320cpu_mod.cfg
+eir.cfg                           spear310evb20.cfg
-ek-lm3s1968.cfg                   steval_pcc010.cfg
+ek-lm3s1968.cfg                   spear310evb20_mod.cfg
-ek-lm3s3748.cfg                   stm320518_eval_stlink.cfg
+ek-lm3s3748.cfg                   spear320cpu.cfg
-ek-lm3s6965.cfg                   stm32100b_eval.cfg
+ek-lm3s6965.cfg                   spear320cpu_mod.cfg
-ek-lm3s811.cfg                    stm3210b_eval.cfg
+ek-lm3s811.cfg                    steval_pcc010.cfg
-ek-lm3s811-revb.cfg               stm3210c_eval.cfg
+ek-lm3s811-revb.cfg               stm320518_eval_stlink.cfg
-ek-lm3s9b9x.cfg                   stm3210e_eval.cfg
+ek-lm3s8962.cfg                   stm32100b_eval.cfg
+ek-lm3s9b9x.cfg                   stm3210b_eval.cfg
+ek-lm3s9d92.cfg                   stm3210c_eval.cfg
+ek-lm4f120xl.cfg                  stm3210e_eval.cfg
 ek-lm4f232.cfg                    stm3220g_eval.cfg
 embedded-artists_lpc2478-32.cfg   stm3220g_eval_stlink.cfg
 ethernut3.cfg                     stm3241g_eval.cfg
 glyn_tonga2.cfg                   stm3241g_eval_stlink.cfg
 hammer.cfg                        stm32f0discovery.cfg
-hilscher_nxdb500sys.cfg           stm32f4discovery.cfg
+hilscher_nxdb500sys.cfg           stm32f3discovery.cfg
-hilscher_nxeb500hmi.cfg           stm32ldiscovery.cfg
+hilscher_nxeb500hmi.cfg           stm32f4discovery.cfg
-hilscher_nxhx10.cfg               stm32vldiscovery.cfg
+hilscher_nxhx10.cfg               stm32ldiscovery.cfg
-hilscher_nxhx500.cfg              str910-eval.cfg
+hilscher_nxhx500.cfg              stm32vldiscovery.cfg
-hilscher_nxhx50.cfg               telo.cfg
+hilscher_nxhx50.cfg               str910-eval.cfg
-hilscher_nxsb100.cfg              ti_beagleboard.cfg
+hilscher_nxsb100.cfg              telo.cfg
-hitex_lpc2929.cfg                 ti_beagleboard_xm.cfg
+hitex_lpc1768stick.cfg            ti_am335xevm.cfg
-hitex_stm32-performancestick.cfg  ti_beaglebone.cfg
+hitex_lpc2929.cfg                 ti_beagleboard.cfg
-hitex_str9-comstick.cfg           ti_blaze.cfg
+hitex_stm32-performancestick.cfg  ti_beagleboard_xm.cfg
-iar_lpc1768.cfg                   ti_pandaboard.cfg
+hitex_str9-comstick.cfg           ti_beaglebone.cfg
-iar_str912_sk.cfg                 ti_pandaboard_es.cfg
+iar_lpc1768.cfg                   ti_blaze.cfg
-icnova_imx53_sodimm.cfg           topas910.cfg
+iar_str912_sk.cfg                 ti_pandaboard.cfg
-icnova_sam9g45_sodimm.cfg         topasa900.cfg
+icnova_imx53_sodimm.cfg           ti_pandaboard_es.cfg
-imx27ads.cfg                      twr-k60n512.cfg
+icnova_sam9g45_sodimm.cfg         topas910.cfg
-imx27lnst.cfg                     tx25_stk5.cfg
+imx27ads.cfg                      topasa900.cfg
-imx28evk.cfg                      tx27_stk5.cfg
+imx27lnst.cfg                     twr-k60f120m.cfg
-imx31pdk.cfg                      unknown_at91sam9260.cfg
+imx28evk.cfg                      twr-k60n512.cfg
-imx35pdk.cfg                      uptech_2410.cfg
+imx31pdk.cfg                      tx25_stk5.cfg
-imx53loco.cfg                     verdex.cfg
+imx35pdk.cfg                      tx27_stk5.cfg
-keil_mcb1700.cfg                  voipac.cfg
+imx53loco.cfg                     unknown_at91sam9260.cfg
-keil_mcb2140.cfg                  voltcraft_dso-3062c.cfg
+keil_mcb1700.cfg                  uptech_2410.cfg
-kwikstik.cfg                      x300t.cfg
+keil_mcb2140.cfg                  verdex.cfg
-linksys_nslu2.cfg                 zy1000.cfg
+kwikstik.cfg                      voipac.cfg
-lisa-l.cfg
+linksys_nslu2.cfg                 voltcraft_dso-3062c.cfg
+lisa-l.cfg                        x300t.cfg
+logicpd_imx27.cfg                 zy1000.cfg
 $
 @end example
 @item @file{target} ...
@@ -1374,71 +1404,83 @@ When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
 the target config file defines all of them.
 @example
 $ ls target
-$duc702x.cfg                       ixp42x.cfg
+aduc702x.cfg                       lpc1763.cfg
-am335x.cfg                         k40.cfg
+am335x.cfg                         lpc1764.cfg
-amdm37x.cfg                        k60.cfg
+amdm37x.cfg                        lpc1765.cfg
-ar71xx.cfg                         lpc1768.cfg
+ar71xx.cfg                         lpc1766.cfg
-at32ap7000.cfg                     lpc2103.cfg
+at32ap7000.cfg                     lpc1767.cfg
-at91r40008.cfg                     lpc2124.cfg
+at91r40008.cfg                     lpc1768.cfg
-at91rm9200.cfg                     lpc2129.cfg
+at91rm9200.cfg                     lpc1769.cfg
-at91sam3ax_4x.cfg                  lpc2148.cfg
+at91sam3ax_4x.cfg                  lpc1788.cfg
-at91sam3ax_8x.cfg                  lpc2294.cfg
+at91sam3ax_8x.cfg                  lpc17xx.cfg
-at91sam3ax_xx.cfg                  lpc2378.cfg
+at91sam3ax_xx.cfg                  lpc1850.cfg
-at91sam3nXX.cfg                    lpc2460.cfg
+at91sam3nXX.cfg                    lpc2103.cfg
-at91sam3sXX.cfg                    lpc2478.cfg
+at91sam3sXX.cfg                    lpc2124.cfg
-at91sam3u1c.cfg                    lpc2900.cfg
+at91sam3u1c.cfg                    lpc2129.cfg
-at91sam3u1e.cfg                    lpc2xxx.cfg
+at91sam3u1e.cfg                    lpc2148.cfg
-at91sam3u2c.cfg                    lpc3131.cfg
+at91sam3u2c.cfg                    lpc2294.cfg
-at91sam3u2e.cfg                    lpc3250.cfg
+at91sam3u2e.cfg                    lpc2378.cfg
-at91sam3u4c.cfg                    lpc4350.cfg
+at91sam3u4c.cfg                    lpc2460.cfg
-at91sam3u4e.cfg                    mc13224v.cfg
+at91sam3u4e.cfg                    lpc2478.cfg
-at91sam3uxx.cfg                    nuc910.cfg
+at91sam3uxx.cfg                    lpc2900.cfg
-at91sam3XXX.cfg                    omap2420.cfg
+at91sam3XXX.cfg                    lpc2xxx.cfg
-at91sam4sXX.cfg                    omap3530.cfg
+at91sam4sd32x.cfg                  lpc3131.cfg
-at91sam4XXX.cfg                    omap4430.cfg
+at91sam4sXX.cfg                    lpc3250.cfg
-at91sam7se512.cfg                  omap4460.cfg
+at91sam4XXX.cfg                    lpc4350.cfg
-at91sam7sx.cfg                     omap5912.cfg
+at91sam7se512.cfg                  lpc4350.cfg.orig
-at91sam7x256.cfg                   omapl138.cfg
+at91sam7sx.cfg                     mc13224v.cfg
-at91sam7x512.cfg                   pic32mx.cfg
+at91sam7x256.cfg                   nuc910.cfg
-at91sam9260.cfg                    pxa255.cfg
+at91sam7x512.cfg                   omap2420.cfg
-at91sam9260_ext_RAM_ext_flash.cfg  pxa270.cfg
+at91sam9260.cfg                    omap3530.cfg
-at91sam9261.cfg                    pxa3xx.cfg
+at91sam9260_ext_RAM_ext_flash.cfg  omap4430.cfg
-at91sam9263.cfg                    readme.txt
+at91sam9261.cfg                    omap4460.cfg
-at91sam9.cfg                       samsung_s3c2410.cfg
+at91sam9263.cfg                    omap5912.cfg
-at91sam9g10.cfg                    samsung_s3c2440.cfg
+at91sam9.cfg                       omapl138.cfg
-at91sam9g20.cfg                    samsung_s3c2450.cfg
+at91sam9g10.cfg                    pic32mx.cfg
-at91sam9g45.cfg                    samsung_s3c4510.cfg
+at91sam9g20.cfg                    pxa255.cfg
-at91sam9rl.cfg                     samsung_s3c6410.cfg
+at91sam9g45.cfg                    pxa270.cfg
-atmega128.cfg                      sharp_lh79532.cfg
+at91sam9rl.cfg                     pxa3xx.cfg
-avr32.cfg                          smp8634.cfg
+atmega128.cfg                      readme.txt
-c100.cfg                           spear3xx.cfg
+avr32.cfg                          samsung_s3c2410.cfg
-c100config.tcl                     stellaris.cfg
+c100.cfg                           samsung_s3c2440.cfg
-c100helper.tcl                     stm32.cfg
+c100config.tcl                     samsung_s3c2450.cfg
-c100regs.tcl                       stm32f0x_stlink.cfg
+c100helper.tcl                     samsung_s3c4510.cfg
-cs351x.cfg                         stm32f1x.cfg
+c100regs.tcl                       samsung_s3c6410.cfg
-davinci.cfg                        stm32f1x_stlink.cfg
+cs351x.cfg                         sharp_lh79532.cfg
-dragonite.cfg                      stm32f2x.cfg
+davinci.cfg                        smp8634.cfg
-dsp56321.cfg                       stm32f2x_stlink.cfg
+dragonite.cfg                      spear3xx.cfg
-dsp568013.cfg                      stm32f2xxx.cfg
+dsp56321.cfg                       stellaris.cfg
-dsp568037.cfg                      stm32f4x.cfg
+dsp568013.cfg                      stellaris_icdi.cfg
-epc9301.cfg                        stm32f4x_stlink.cfg
+dsp568037.cfg                      stm32f0x_stlink.cfg
-faux.cfg                           stm32l.cfg
+efm32_stlink.cfg                   stm32f1x.cfg
-feroceon.cfg                       stm32lx_stlink.cfg
+epc9301.cfg                        stm32f1x_stlink.cfg
-fm3.cfg                            stm32_stlink.cfg
+faux.cfg                           stm32f2x.cfg
-hilscher_netx10.cfg                stm32xl.cfg
+feroceon.cfg                       stm32f2x_stlink.cfg
-hilscher_netx500.cfg               str710.cfg
+fm3.cfg                            stm32f3x.cfg
-hilscher_netx50.cfg                str730.cfg
+hilscher_netx10.cfg                stm32f3x_stlink.cfg
-icepick.cfg                        str750.cfg
+hilscher_netx500.cfg               stm32f4x.cfg
-imx21.cfg                          str912.cfg
+hilscher_netx50.cfg                stm32f4x_stlink.cfg
-imx25.cfg                          swj-dp.tcl
+icepick.cfg                        stm32l.cfg
-imx27.cfg                          test_reset_syntax_error.cfg
+imx21.cfg                          stm32lx_dual_bank.cfg
-imx28.cfg                          test_syntax_error.cfg
+imx25.cfg                          stm32lx_stlink.cfg
-imx31.cfg                          ti_dm355.cfg
+imx27.cfg                          stm32_stlink.cfg
-imx35.cfg                          ti_dm365.cfg
+imx28.cfg                          stm32w108_stlink.cfg
-imx51.cfg                          ti_dm6446.cfg
+imx31.cfg                          stm32xl.cfg
-imx53.cfg                          tmpa900.cfg
+imx35.cfg                          str710.cfg
-imx.cfg                            tmpa910.cfg
+imx51.cfg                          str730.cfg
-is5114.cfg                         u8500.cfg
+imx53.cfg                          str750.cfg
+imx6.cfg                           str912.cfg
+imx.cfg                            swj-dp.tcl
+is5114.cfg                         test_reset_syntax_error.cfg
+ixp42x.cfg                         test_syntax_error.cfg
+k40.cfg                            ti-ar7.cfg
+k60.cfg                            ti_calypso.cfg
+lpc1751.cfg                        ti_dm355.cfg
+lpc1752.cfg                        ti_dm365.cfg
+lpc1754.cfg                        ti_dm6446.cfg
+lpc1756.cfg                        tmpa900.cfg
+lpc1758.cfg                        tmpa910.cfg
+lpc1759.cfg                        u8500.cfg
 @end example
 @item @emph{more} ... browse for other library files which may be useful.
 For example, there are various generic and CPU-specific utilities.
@@ -1878,14 +1920,14 @@ After setting targets, you can define a list of targets working in SMP.
 @example
 set _TARGETNAME_1 $_CHIPNAME.cpu1
 set _TARGETNAME_2 $_CHIPNAME.cpu2
-target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
 -coreid 0 -dbgbase $_DAP_DBG1
-target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
 -coreid 1 -dbgbase $_DAP_DBG2
 #define 2 targets working in smp.
 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
 @end example
-In the above example on cortex_a8, 2 cpus are working in SMP.
+In the above example on cortex_a, 2 cpus are working in SMP.
 In SMP only one GDB instance is created and :
 @itemize @bullet
 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
@@ -1896,32 +1938,32 @@ In SMP only one GDB instance is created and :
 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
 @end itemize
 
-The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
+The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
 command have been implemented.
 @itemize @bullet
-@item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
+@item cortex_a smp_on : enable SMP mode, behaviour is as described above.
-@item cortex_a8 smp_off : disable SMP mode, the current target is the one
+@item cortex_a smp_off : disable SMP mode, the current target is the one
 displayed in the GDB session, only this target is now controlled by GDB
 session. This behaviour is useful during system boot up.
-@item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
+@item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
 following example.
 @end itemize
 
 @example
->cortex_a8 smp_gdb
+>cortex_a smp_gdb
 gdb coreid  0 -> -1
 #0 : coreid 0 is displayed to GDB ,
 #-> -1 : next resume triggers a real resume
-> cortex_a8 smp_gdb 1
+> cortex_a smp_gdb 1
 gdb coreid  0 -> 1
 #0 :coreid 0 is displayed to GDB ,
 #->1  : next resume displays coreid 1 to GDB
 > resume
-> cortex_a8 smp_gdb
+> cortex_a smp_gdb
 gdb coreid  1 -> 1
 #1 :coreid 1 is displayed to GDB ,
 #->1 : next resume displays coreid 1 to GDB
-> cortex_a8 smp_gdb -1
+> cortex_a smp_gdb -1
 gdb coreid  1 -> -1
 #1 :coreid 1 is displayed to GDB,
 #->-1 : next resume triggers a real resume
@@ -1948,7 +1990,7 @@ don't want to reset all targets at once.
 Such a handler might write to chip registers to force a reset,
 use a JRC to do that (preferable -- the target may be wedged!),
 or force a watchdog timer to trigger.
-(For Cortex-M3 targets, this is not necessary. The target
+(For Cortex-M targets, this is not necessary.  The target
 driver knows how to use trigger an NVIC reset when SRST is
 not available.)
 
@@ -3953,7 +3995,7 @@ look like with more than one:
     TargetName         Type       Endian TapName            State
 --  ------------------ ---------- ------ ------------------ ------------
  0* at91rm9200.cpu     arm920t    little at91rm9200.cpu     running
- 1  MyTarget           cortex_m3  little mychip.foo         tap-disabled
+ 1  MyTarget           cortex_m   little mychip.foo         tap-disabled
 @end verbatim
 
 One member of that list is the @dfn{current target}, which
@@ -4064,8 +4106,8 @@ At this writing, the supported CPU types and variants are:
 @item @code{arm9tdmi} -- this is an ARMv4 core
 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
 (Support for this is preliminary and incomplete.)
-@item @code{cortex_a8} -- this is an ARMv7 core with an MMU
+@item @code{cortex_a} -- this is an ARMv7 core with an MMU
-@item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
+@item @code{cortex_m} -- this is an ARMv7 core, supporting only the
 compact Thumb2 instruction set.
 @item @code{dragonite} -- resembles arm966e
 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
@@ -4119,7 +4161,7 @@ to be much more board-specific.
 The key steps you use might look something like this
 
 @example
-target create MyTarget cortex_m3 -chain-position mychip.cpu
+target create MyTarget cortex_m -chain-position mychip.cpu
 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
 $MyTarget configure -event reset-init @{ myboard_reinit @}
@@ -5014,8 +5056,9 @@ supported.}
 @end deffn
 
 @deffn {Flash Driver} lpc2000
-Most members of the LPC1700 and LPC2000 microcontroller families from NXP
+Most members of the LPC1700, LPC1800, LPC2000 and LPC4300 microcontroller
-include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
+families from NXP include internal flash and use Cortex-M3 (LPC1700, LPC1800),
+Cortex-M4 (LPC4300) or ARM7TDMI (LPC2000) cores.
 
 @quotation Note
 There are LPC2000 devices which are not supported by the @var{lpc2000}
@@ -5031,7 +5074,9 @@ which must appear in the following order:
 @item @var{variant} ... required, may be
 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
-or @option{lpc1700} (LPC175x and LPC176x)
+@option{lpc1700} (LPC175x and LPC176x)
+or @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
+LPC43x[2357])
 @item @var{clock_kHz} ... the frequency, in kiloHertz,
 at which the core is running
 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
@@ -7297,7 +7342,7 @@ cores @emph{except the ARM1176} use the same six bits.
 @cindex Debug Access Port
 @cindex DAP
 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
-included on Cortex-M3 and Cortex-A8 systems.
+included on Cortex-M and Cortex-A systems.
 They are available in addition to other core-specific commands that may be available.
 
 @deffn Command {dap apid} [num]
@@ -7330,10 +7375,10 @@ fix CSW_SPROT from register AP_REG_CSW on selected dap.
 Defaulting to 0.
 @end deffn
 
-@subsection Cortex-M3 specific commands
+@subsection Cortex-M specific commands
-@cindex Cortex-M3
+@cindex Cortex-M
 
-@deffn Command {cortex_m3 maskisr} (@option{auto}|@option{on}|@option{off})
+@deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
 Control masking (disabling) interrupts during target step/resume.
 
 The @option{auto} option handles interrupts during stepping a way they get
@@ -7350,7 +7395,7 @@ with interrupts enabled, i.e. the same way the @option{off} option does.
 Default is @option{auto}.
 @end deffn
 
-@deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
+@deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
 @cindex vector_catch
 Vector Catch hardware provides dedicated breakpoints
 for certain hardware events.
@@ -7377,7 +7422,7 @@ must also be explicitly enabled.
 This finishes by listing the current vector catch configuration.
 @end deffn
 
-@deffn Command {cortex_m3 reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
+@deffn Command {cortex_m reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
 Control reset handling. The default @option{srst} is to use srst if fitted,
 otherwise fallback to @option{vectreset}.
 @itemize @minus
@@ -7385,7 +7430,7 @@ otherwise fallback to @option{vectreset}.
 @item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
 @item @option{vectreset} use NVIC VECTRESET to reset system.
 @end itemize
-Using @option{vectreset} is a safe option for all current Cortex-M3 cores.
+Using @option{vectreset} is a safe option for all current Cortex-M cores.
 This however has the disadvantage of only resetting the core, all peripherals
 are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
 the peripherals.
@@ -7404,7 +7449,7 @@ The most powerful mechanism is semihosting, but there is also
 a lighter weight mechanism using only the DCC channel.
 
 Currently @command{target_request debugmsgs}
-is supported only for @option{arm7_9} and @option{cortex_m3} cores.
+is supported only for @option{arm7_9} and @option{cortex_m} cores.
 These messages are received as part of target polling, so
 you need to have @command{poll on} active to receive them.
 They are intrusive in that they will affect program execution
@@ -7910,10 +7955,10 @@ and an RTOS until he told GDB to disable the IRQs while stepping:
 
 @example
 define hook-step
-mon cortex_m3 maskisr on
+mon cortex_m maskisr on
 end
 define hookpost-step
-mon cortex_m3 maskisr off
+mon cortex_m maskisr off
 end
 @end example
 

src/flash/nor/kinetis.c

@@ -365,23 +365,27 @@ static int kinetis_write(struct flash_bank *bank, uint8_t *buffer,
 
 	/* program section command */
 	if (fallback == 0) {
-		unsigned prog_section_bytes = kinfo->sector_size >> 8;
-		for (i = 0; i < count; i += kinfo->sector_size) {
 		/*
-			 * The largest possible Kinetis "section" is
+		 * Kinetis uses different terms for the granularity of
-			 * 16 bytes.  A full Kinetis sector is always
+		 * sector writes, e.g. "phrase" or "128 bits".  We use
-			 * 256 "section"s.
+		 * the generic term "chunk". The largest possible
+		 * Kinetis "chunk" is 16 bytes (128 bits).
 		 */
+		unsigned prog_section_chunk_bytes = kinfo->sector_size >> 8;
+		/* assume the NVM sector size is half the FlexRAM size */
+		unsigned prog_size_bytes = MIN(kinfo->sector_size,
+					       kinetis_flash_params[kinfo->granularity].nvm_sector_size_bytes);
+		for (i = 0; i < count; i += prog_size_bytes) {
 			uint8_t residual_buffer[16];
 			uint8_t ftfx_fstat;
-			uint32_t section_count = 256;
+			uint32_t section_count = prog_size_bytes / prog_section_chunk_bytes;
 			uint32_t residual_wc = 0;
 
 			/*
 			 * Assume the word count covers an entire
 			 * sector.
 			 */
-			wc = kinfo->sector_size / 4;
+			wc = prog_size_bytes / 4;
 
 			/*
 			 * If bytes to be programmed are less than the
@@ -390,21 +394,21 @@ static int kinetis_write(struct flash_bank *bank, uint8_t *buffer,
 			 * residual buffer so that a full "section"
 			 * may always be programmed.
 			 */
-			if ((count - i) < kinfo->sector_size) {
+			if ((count - i) < prog_size_bytes) {
 				/* number of bytes to program beyond full section */
-				unsigned residual_bc = (count-i) % prog_section_bytes;
+				unsigned residual_bc = (count-i) % prog_section_chunk_bytes;
 
 				/* number of complete words to copy directly from buffer */
 				wc = (count - i) / 4;
 
 				/* number of total sections to write, including residual */
-				section_count = DIV_ROUND_UP((count-i), prog_section_bytes);
+				section_count = DIV_ROUND_UP((count-i), prog_section_chunk_bytes);
 
 				/* any residual bytes delivers a whole residual section */
-				residual_wc = (residual_bc ? prog_section_bytes : 0)/4;
+				residual_wc = (residual_bc ? prog_section_chunk_bytes : 0)/4;
 
 				/* clear residual buffer then populate residual bytes */
-				(void) memset(residual_buffer, 0xff, prog_section_bytes);
+				(void) memset(residual_buffer, 0xff, prog_section_chunk_bytes);
 				(void) memcpy(residual_buffer, &buffer[i+4*wc], residual_bc);
 			}
 
@@ -770,7 +774,7 @@ static int kinetis_blank_check(struct flash_bank *bank)
 			for (i = 0; i < bank->num_sectors; i++) {
 				/* normal margin */
 				result = kinetis_ftfx_command(bank, FTFx_CMD_SECTSTAT, bank->base + bank->sectors[i].offset,
-						0, 0, 0, 1,  0, 0, 0, 0, &ftfx_fstat);
+						1, 0, 0, 0,  0, 0, 0, 0, &ftfx_fstat);
 
 				if (result == ERROR_OK) {
 					bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);

src/jtag/drivers/ft2232.c

@@ -3141,9 +3141,8 @@ static void flossjtag_blink(void)
 static int ft2232_quit(void)
 {
 #if BUILD_FT2232_FTD2XX == 1
-	FT_STATUS status;
 
-	status = FT_Close(ftdih);
+	FT_Close(ftdih);
 #elif BUILD_FT2232_LIBFTDI == 1
 	ftdi_usb_close(&ftdic);
 

src/rtos/ChibiOS.c

@@ -94,7 +94,7 @@ struct ChibiOS_params {
 
 struct ChibiOS_params ChibiOS_params_list[] = {
 	{
-	"cortex_m3",							/* target_name */
+	"cortex_m",							/* target_name */
 	0,
 	NULL,									/* stacking_info */
 	},

src/rtos/FreeRTOS.c

@@ -50,7 +50,7 @@ struct FreeRTOS_params {
 
 const struct FreeRTOS_params FreeRTOS_params_list[] = {
 	{
-	"cortex_m3",			/* target_name */
+	"cortex_m",			/* target_name */
 	4,						/* thread_count_width; */
 	4,						/* pointer_width; */
 	16,						/* list_next_offset; */

src/rtos/ThreadX.c

@@ -73,7 +73,7 @@ struct ThreadX_params {
 
 const struct ThreadX_params ThreadX_params_list[] = {
 	{
-	"cortex_m3",				/* target_name */
+	"cortex_m",				/* target_name */
 	4,							/* pointer_width; */
 	8,							/* thread_stack_offset; */
 	40,							/* thread_name_offset; */

src/rtos/eCos.c

@@ -64,7 +64,7 @@ struct eCos_params {
 
 const struct eCos_params eCos_params_list[] = {
 	{
-	"cortex_m3",			/* target_name */
+	"cortex_m",			/* target_name */
 	4,						/* pointer_width; */
 	0x0c,					/* thread_stack_offset; */
 	0x9c,					/* thread_name_offset; */

src/server/gdb_server.c

@@ -1259,7 +1259,7 @@ static int gdb_write_memory_packet(struct connection *connection,
 
 	LOG_DEBUG("addr: 0x%8.8" PRIx32 ", len: 0x%8.8" PRIx32 "", addr, len);
 
-	if (unhexify((char *)buffer, separator + 2, len) != (int)len)
+	if (unhexify((char *)buffer, separator, len) != (int)len)
 		LOG_ERROR("unable to decode memory packet");
 
 	retval = target_write_buffer(target, addr, len, buffer);

src/target/arm11.c

@@ -1094,6 +1094,7 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
 	if (!arm11)
 		return ERROR_FAIL;
 
+	arm11->arm.core_type = ARM_MODE_ANY;
 	arm_init_arch_info(target, &arm11->arm);
 
 	arm11->jtag_info.tap = target->tap;

src/target/arm7_9_common.c

@@ -2806,6 +2806,7 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
 	arm7_9->dcc_downloads = false;
 
 	arm->arch_info = arm7_9;
+	arm->core_type = ARM_MODE_ANY;
 	arm->read_core_reg = arm7_9_read_core_reg;
 	arm->write_core_reg = arm7_9_write_core_reg;
 	arm->full_context = arm7_9_full_context;

src/target/cortex_a.c

@@ -2746,9 +2746,9 @@ static const struct command_registration cortex_a8_command_handlers[] = {
 		.chain = armv7a_command_handlers,
 	},
 	{
-		.name = "cortex_a8",
+		.name = "cortex_a",
 		.mode = COMMAND_ANY,
-		.help = "Cortex-A8 command group",
+		.help = "Cortex-A command group",
 		.usage = "",
 		.chain = cortex_a8_exec_command_handlers,
 	},

src/target/cortex_m.c

@@ -1796,6 +1796,9 @@ fail1:
 		for (j = 0; j < 3; j++, reg++)
 			cortex_m3_dwt_addreg(target, cache->reg_list + reg,
 				dwt_comp + 3 * i + j);
+
+		/* make sure we clear any watchpoints enabled on the target */
+		target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
 	}
 
 	*register_get_last_cache_p(&target->reg_cache) = cache;
@@ -1887,6 +1890,9 @@ int cortex_m3_examine(struct target *target)
 			cortex_m3->fp_comparator_list[i].type =
 				(i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
 			cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
+
+			/* make sure we clear any breakpoints enabled on the target */
+			target_write_u32(target, cortex_m3->fp_comparator_list[i].fpcr_address, 0);
 		}
 		LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
 			fpcr,
@@ -2250,9 +2256,9 @@ static const struct command_registration cortex_m3_command_handlers[] = {
 		.chain = armv7m_command_handlers,
 	},
 	{
-		.name = "cortex_m3",
+		.name = "cortex_m",
 		.mode = COMMAND_EXEC,
-		.help = "Cortex-M3 command group",
+		.help = "Cortex-M command group",
 		.usage = "",
 		.chain = cortex_m3_exec_command_handlers,
 	},
@@ -2260,7 +2266,8 @@ static const struct command_registration cortex_m3_command_handlers[] = {
 };
 
 struct target_type cortexm3_target = {
-	.name = "cortex_m3",
+	.name = "cortex_m",
+	.deprecated_name = "cortex_m3",
 
 	.poll = cortex_m3_poll,
 	.arch_state = armv7m_arch_state,

src/target/startup.tcl

@@ -167,3 +167,14 @@ proc init_targets {} {
 # Additionally board config scripts can define a procedure init_board that will be executed after init and init_targets
 proc init_board {} {
 }
+
+# deprecated target name cmds
+proc cortex_m3 args {
+	echo "DEPRECATED! use 'cortex_m' not 'cortex_m3'"
+	eval cortex_m $args
+}
+
+proc cortex_a8 args {
+	echo "DEPRECATED! use 'cortex_a' not 'cortex_a8'"
+	eval cortex_a $args
+}

src/target/xscale.c

@@ -2997,6 +2997,7 @@ static int xscale_init_arch_info(struct target *target,
 
 	/* prepare ARMv4/5 specific information */
 	arm->arch_info = xscale;
+	arm->core_type = ARM_MODE_ANY;
 	arm->read_core_reg = xscale_read_core_reg;
 	arm->write_core_reg = xscale_write_core_reg;
 	arm->full_context = xscale_full_context;

tcl/board/icnova_imx53_sodimm.cfg

@@ -19,7 +19,7 @@ adapter_khz 3000
 
 $_TARGETNAME configure -event "reset-assert" {
 	echo "Reseting ...."
-	#cortex_a8 dbginit
+	#cortex_a dbginit
 }
 
 $_TARGETNAME configure -event reset-init { sodimm_init }

tcl/board/imx53loco.cfg

@@ -20,7 +20,7 @@ adapter_khz 3000
 
 $_TARGETNAME configure -event "reset-assert" {
 	echo "Reseting ...."
-	#cortex_a8 dbginit
+	#cortex_a dbginit
 }
 
 $_TARGETNAME configure -event reset-init { loco_init }

tcl/target/am335x.cfg

@@ -55,7 +55,7 @@ if { [info exists JRC_TAPID ] } {
 } else {
    set _JRC_TAPID 0x0b94402f
 }
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
 jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
 # some TCK tycles are required to activate the DEBUG power domain
 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
@@ -64,13 +64,13 @@ jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
 # Cortex A8 target
 #
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
 
 # SRAM: 64K at 0x4030.0000; use the first 16K
 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
 
 $_TARGETNAME configure -event gdb-attach {
-   cortex_a8 dbginit
+   cortex_a dbginit
    halt
 }
 

tcl/target/amdm37x.cfg

@@ -141,7 +141,7 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
 
 # Create the CPU target to be used with GDB:  Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
 
 # The DM37x has 64K of SRAM starting at address 0x4020_0000.  Allow the first
 # 16K to be used as a scratchpad for OpenOCD.
@@ -200,7 +200,7 @@ $_TARGETNAME configure -event gdb-attach {
 # reset sequence.
 proc amdm37x_dbginit {target} {
    # General Cortex A8 debug initialisation
-   cortex_a8 dbginit
+   cortex_a dbginit
 
    # Enable DBGEN signal.  This signal is described in the ARM v7 TRM, but
    # access to the signal appears to be implementation specific.  TI does not

tcl/target/at91sam3XXX.cfg

@@ -58,7 +58,7 @@ if { [info exists CPUTAPID] } {
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # 16K is plenty, the smallest chip has this much
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
@@ -69,4 +69,4 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/at91sam3nXX.cfg

@@ -18,12 +18,12 @@ if { [info exists CPUTAPID] } {
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian little -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq
 

tcl/target/at91sam4XXX.cfg

@@ -35,7 +35,7 @@ if { [info exists CPUTAPID] } {
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # 16K is plenty, the smallest chip has this much
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
@@ -46,4 +46,4 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/fm3.cfg

@@ -29,7 +29,7 @@ reset_config trst_only
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # MB9BF506 has 64kB of SRAM on its main system bus 
 $_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
@@ -44,4 +44,4 @@ adapter_khz 500
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/imx51.cfg

@@ -31,7 +31,7 @@ jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
 
 # GDB target: Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
 
 # some TCK tycles are required to activate the DEBUG power domain
 jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
@@ -41,7 +41,7 @@ jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
 
 proc imx51_dbginit {target} {
      # General Cortex A8 debug initialisation
-     cortex_a8 dbginit
+     cortex_a dbginit
 }
 
 # Slow speed to be sure it will work

tcl/target/imx53.cfg

@@ -31,7 +31,7 @@ jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
 
 # GDB target: Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
 
 # some TCK tycles are required to activate the DEBUG power domain
 jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
@@ -41,7 +41,7 @@ jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
 
 proc imx53_dbginit {target} {
      # General Cortex A8 debug initialisation
-     cortex_a8 dbginit
+     cortex_a dbginit
 }
 
 # Slow speed to be sure it will work

tcl/target/k40.cfg

@@ -29,11 +29,11 @@ set _TARGETNAME $_CHIPNAME.cpu
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
 
 $_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
 $_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/k60.cfg

@@ -29,11 +29,11 @@ set _TARGETNAME $_CHIPNAME.cpu
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
 
 $_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
 $_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/lpc1788.cfg

@@ -17,4 +17,4 @@ set CCLK 12000
 source [find target/lpc17xx.cfg];
 
 # if srst is not fitted, use SYSRESETREQ to perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/lpc17xx.cfg

@@ -57,7 +57,7 @@ jtag_ntrst_delay 200
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
 
 # The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
@@ -94,4 +94,4 @@ $_TARGETNAME configure -event reset-init {
 
 # if srst is not fitted use VECTRESET to
 # perform a soft reset - SYSRESETREQ is not supported
-cortex_m3 reset_config vectreset
+cortex_m reset_config vectreset

tcl/target/lpc1850.cfg

@@ -24,8 +24,8 @@ if { [info exists M3_JTAG_TAPID] } {
 jtag newtap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
 
 set _TARGETNAME $_CHIPNAME.m3
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/lpc4350.cfg

@@ -40,12 +40,12 @@ jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
 jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
 				-expected-id $_M0_JTAG_TAPID
 
-target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
-target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0
+target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
 
 # on this CPU we should use VECTRESET to perform a soft reset and
 # manually reset the periphery
 # SRST or SYSRESETREQ disable the debug interface for the time of
 # the reset and will not fit our requirements for a consistent debug
 # session
-cortex_m3 reset_config vectreset
+cortex_m reset_config vectreset

tcl/target/omap3530.cfg

@@ -36,7 +36,7 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
 
 # GDB target: Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
 
 # SRAM: 64K at 0x4020.0000; use the first 16K
 $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
@@ -54,7 +54,7 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
 
 proc omap3_dbginit {target} {
      # General Cortex A8 debug initialisation
-     cortex_a8 dbginit
+     cortex_a dbginit
      # Enable DBGU signal for OMAP353x
      $target mww phys 0x5401d030 0x00002000
 }

tcl/target/omap4430.cfg

@@ -94,7 +94,7 @@ set _coreid 0
 set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
 echo "Using dbgbase = [format 0x%x $_dbgbase]"
  
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
   -coreid 0 -dbgbase $_dbgbase
 
 # SRAM: 56KiB at 0x4030.0000
@@ -104,8 +104,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
 #
 # M3 targets, separate TAP/DAP for each core
 #
-target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
-target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap
+target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
 
 
 # Once the JRC is up, enable our TAPs

tcl/target/omap4460.cfg

@@ -94,7 +94,7 @@ set _coreid 0
 set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
 echo "Using dbgbase = [format 0x%x $_dbgbase]"
 
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
   -coreid 0 -dbgbase $_dbgbase
 
 # SRAM: 56KiB at 0x4030.0000
@@ -104,8 +104,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
 #
 # M3 targets, separate TAP/DAP for each core
 #
-target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
-target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap
+target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
 
 
 # Once the JRC is up, enable our TAPs

tcl/target/omapl138.cfg

@@ -35,7 +35,7 @@ if { [info exists JRC_TAPID] } {
 } else {
    set _JRC_TAPID 0x0b7d102f
 }
-jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
 
 jtag configure $_CHIPNAME.jrc -event setup \
 	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"

tcl/target/stellaris.cfg

@@ -52,7 +52,7 @@ if { [info exists WORKAREASIZE] } {
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
 
 # 8K working area at base of ram, not backed up
 #
@@ -157,11 +157,11 @@ $_TARGETNAME configure -event reset-start {
 	if {$device_class == 0 || $device_class == 1 ||
 		$device_class == 3 || $device_class == 5} {
 		# Sandstorm, Fury, DustDevil and Blizzard are able to use NVIC SYSRESETREQ
-		cortex_m3 reset_config sysresetreq
+		cortex_m reset_config sysresetreq
 	} else {
 		# Tempest and Firestorm default to using NVIC VECTRESET
 		# peripherals will need reseting manually, see proc reset_peripherals
-		cortex_m3 reset_config vectreset
+		cortex_m reset_config vectreset
 
 		# reset peripherals, based on code in
 		# http://www.ti.com/lit/er/spmz573a/spmz573a.pdf

tcl/target/stm32f1x.cfg

@@ -68,7 +68,7 @@ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
 	-expected-id $_BSTAPID8 -expected-id $_BSTAPID9
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -78,4 +78,4 @@ flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/stm32f2x.cfg

@@ -52,7 +52,7 @@ if { [info exists BSTAPID] } {
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -61,4 +61,4 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/stm32f3x.cfg

@@ -52,7 +52,7 @@ if { [info exists BSTAPID] } {
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -61,4 +61,4 @@ flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/stm32f4x.cfg

@@ -51,7 +51,7 @@ if { [info exists BSTAPID] } {
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -60,4 +60,4 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

tcl/target/stm32l.cfg

@@ -48,7 +48,7 @@ if { [info exists BSTAPID] } {
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -59,7 +59,7 @@ flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq
 
 proc stm32l_enable_HSI {} {
 	# Enable HSI as clock source

tcl/target/u8500.cfg

@@ -19,12 +19,12 @@ proc ocd_gdb_restart {target_id} {
 	global _SMP
     targets $_TARGETNAME_1
 	if { [expr ($_SMP == 1)] } {
-	cortex_a8 smp_off
+	cortex_a smp_off
 	}
 	rst_run
 	halt
 	if { [expr ($_SMP == 1)]} {
-	cortex_a8 smp_on
+	cortex_a smp_on
 	}
 }
 
@@ -202,7 +202,7 @@ if { [info exists DAP_DBG2] } {
 	set _DAP_DBG2 0x801AA000 
 }
 
-target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
+target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
 
 $_TARGETNAME_1 configure -event gdb-attach {
 	halt
@@ -217,7 +217,7 @@ global _TARGETNAME_2
 set _TARGETNAME_2 $TARGETNAME_2
 }
 
-target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
+target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
 
 $_TARGETNAME_2 configure -event gdb-attach {
 	halt