22045fa6f2
When setting up an ETM, cache its ETM_CONFIG register. Then only expose the registers which are actually present. They could be missing for two basic reasons:
dbrownell
2009-09-23 21:52:40 +00:00
d9ce8a2f60
Start cleaning up ETM register handling. On one ARM926 ETM+ETB system, removes 20 non-existent registers ... but still includes over 45 (!) ETM registers which don't even exist there ...
dbrownell
2009-09-23 09:16:00 +00:00
a6d858ebcd
Initial ETM cleanups. Most of these are cosmetic:
dbrownell
2009-09-23 07:49:38 +00:00
7393fcfc90
Nico Coesel <ncoesel@dealogic.nl> fix warnings. . I'm wondering why these didn't turn up earlier. Is everyone still using gcc 3.x? Or is the x86 version of gcc 4.x much more relaxed?
oharboe
2009-09-23 07:14:03 +00:00
6521b75ec2
- fix build issue under win32 (cygwin/msys) from svn r2746
ntfreak
2009-09-22 15:39:23 +00:00
50b94628ae
Make it easier to erase or protect through to the end of a (NOR) flash chip: allow passing "last" as an alias for the number of the last sector.
dbrownell
2009-09-22 05:39:06 +00:00
6cba486356
Update presentation of TAP events and tap enable/disable.
dbrownell
2009-09-21 21:35:56 +00:00
108028112f
Ensure that DaVinci chips can't start with a too-fast JTAG clock. It can be sped up later, once it's known the PLLs are active.
dbrownell
2009-09-21 00:37:58 +00:00
d20103cd93
Update the jtag-examine_chain() logic to verify that there's no garbage after the expected data (from the TAPs' BYPASS or IDCODE registers).
dbrownell
2009-09-21 00:04:35 +00:00
24df719b09
Update the User's Guide to cover the scan chain verification step done on exit from the config stage, how JTAG clocking issues can trigger errors there, and how to avoid such problems.
dbrownell
2009-09-20 21:17:08 +00:00
75581ffea6
Minor regression bugfix for the jtag_tap_handle_event() case for disabling TAPs. We don't actually know how to make any JRCs which do that yet; but when we do, this will matter.
dbrownell
2009-09-20 07:46:22 +00:00
358263f484
Tweak TCL reset script ... mostly improving descriptions of the various steps, but also calling [target names] only once.
dbrownell
2009-09-18 00:11:51 +00:00
e961bd14d9
Address codereview comment from Steve Grubb <sgrubb@redhat.com>: avoid a duplicate test.
dbrownell
2009-09-17 19:20:18 +00:00
9536577c02
Minor fixes to NAND code and docs
dbrownell
2009-09-17 18:56:17 +00:00
9655c5b093
Fix coredump seen in some code paths.
dbrownell
2009-09-17 18:52:32 +00:00
84f51bf50c
michal smulski <michal.smulski@ooma.com> fix regression in jtag_add_pathmove() which broke arm11 in r1825. Other uses of jtag_add_pathmove are svn + xsvf + xscale...
oharboe
2009-09-17 12:25:53 +00:00
1dd302883d
prefix zy1000_reboot command to avoid name conflicts
oharboe
2009-09-17 11:44:14 +00:00
016e7ebbfa
srst_gates_jtag option. at91sam9260 needs retesting, and possibly srst_gates_jtag added to reset_config. Could i.MX27 be a case where srst does not pull trst, but really srst gates jtag clock?
oharboe
2009-09-17 11:23:41 +00:00
cb7ad25c04
The "arm9tdmi.c" file is more of a generic ARM9 support file:
dbrownell
2009-09-17 08:02:43 +00:00
e18bd3b55e
Doc update: mention how ARM's WFI instruction affects JTAG clocking by gating the core clock, and workarounds. Most details are with the "halt" command, which is one of the first places this issue will be noticed.
dbrownell
2009-09-17 07:56:24 +00:00
8e39f86ef4
Rolf Meeser <rolfm_9dq@yahoo.de> warning fix in previous commit was wrong. target_code_size needs the real value later.
oharboe
2009-09-14 07:48:28 +00:00
40f361dd94
David Brownell <david-b@pacbell.net> Update the board config for the DaVinci DM355 EVM so the reset-init event handler does the rest of the work it should do:
oharboe
2009-09-12 08:11:45 +00:00
c993d75d1f
David Brownell <david-b@pacbell.net> Cleanup some the downloaded ARM target algorithm code:
oharboe
2009-09-12 08:10:19 +00:00
f6a29d438e
David Brownell <david-b@pacbell.net> some early todo items on run_algorithm
oharboe
2009-09-11 21:14:31 +00:00
4f7761828c
tap post reset event added. Allows omap3530 to send 100 runtest idle tickle's after a TAP_RESET.
oharboe
2009-09-11 18:34:15 +00:00
ec3015db1a
- revert change made to sheevaplug.cfg in rev2573
ntfreak
2009-09-11 14:08:28 +00:00
25f9a466ca
Nicolas Pitre <nico@cam.org> put feroceon target definition at the end so to avoid a bunch of useless forward declarations.
oharboe
2009-09-11 08:04:50 +00:00
00e900f8a1
Nicolas Pitre <nico@cam.org> Dragonite support
oharboe
2009-09-11 08:03:46 +00:00
3bade442b1
Alexei Babich <a.babich@rez.ru> fix problems with unecessary tailend byte accesses. Use 16 bit access on tailend of a memory read if possible.
oharboe
2009-09-10 13:17:05 +00:00
7b5ddb4a58
Rolf Meeser <rolfm_9dq@yahoo.de> This patch adds target algorithm support for those flash devices that do not support DQ5 polling. So far they could only be programmed with host algorithm, but this was way too slow.
oharboe
2009-09-09 16:11:33 +00:00
983f5a1ae9
- Fix bug-in-waiting when adding more than one TAP event type - Infinite loop bugfix when running tap configure a second time
oharboe
2009-09-09 07:09:14 +00:00
aa46b15377
David Brownell <david-b@pacbell.net> Optionally shave time off the armv4_5 run_algorithm() code: let them terminate using software breakpoints, avoiding roundtrips to manage hardware ones.
oharboe
2009-09-09 06:28:49 +00:00
8b2b0071a9
David Brownell <david-b@pacbell.net> Fix docs on ARM11 MCR and MRC coprocessor commands: correct read-vs-write; and describe the params.
oharboe
2009-09-09 06:27:47 +00:00
857c06ca8b
Report correct core instruction state for ARMv/A targets
mlu
2009-09-08 15:32:18 +00:00
f6a5749c1b
Load PC with bit 0 set to 1 when resuming to say in Thumb instruction state.
mlu
2009-09-08 15:31:24 +00:00
5dae4753ff
David Brownell <david-b@pacbell.net> Provide an "armv7a disassemble" command. Current omissions include VFP (except as coprocessor instructions), Neon, and various Thumb2 opcodes that are not available in ARMv7-M processors.
oharboe
2009-09-08 06:18:45 +00:00
57e12b7e45
David Brownell <david-b@pacbell.net> lean up some loose ends with the ARM disassembler
oharboe
2009-09-08 06:17:33 +00:00
2c76cd7171
Improved handling of instruction set state, helps for debugging Thumb state.
mlu
2009-09-07 20:19:17 +00:00
a690ee3c0c
Mahr, Stefan <Stefan.Mahr@sphairon.com> removes the endianness swapping in mips_m4k.c Swapping is already done in target.c
oharboe
2009-09-04 19:35:10 +00:00
0b11e4dbb4
use "armv4_5 core_state arm" instead of soft_reset_halt, fewer side effects
oharboe
2009-09-04 11:03:26 +00:00
2e29131f2b
set ARM mode using explicit command rather than soft_reset_halt which has lots of side effects.
oharboe
2009-09-04 08:23:24 +00:00
81b57a3fb6
Matt Hsu <matt@0xlab.org> This patch simply enables the halting debug mode. By enabling this bit, the processor halts when a debug event such as breakpoint occurs.
oharboe
2009-09-04 08:22:02 +00:00
ee329275d3
more debug output for breakpoints
oharboe
2009-09-04 08:21:18 +00:00
51be978b43
Matt Hsu <matt@0xlab.org> Tidy up the bit-offset operation for DSCR register
oharboe
2009-09-04 05:20:45 +00:00
072d6d3db6
Dirk Behme <dirk.behme@googlemail.com> Fix typo in help text. It has to be 'production_test' instead of 'production' here.
oharboe
2009-08-30 20:08:07 +00:00
fbe1c23c12
David Brownell <david-b@pacbell.net> Fix Sandstorm revision checking: right bits, right value!
oharboe
2009-08-30 20:05:40 +00:00