# SPDX-License-Identifier: GPL-2.0-or-later
# maxim Integrated OpenOCD target configuration file

# reset pin configuration
reset_config none
adapter_nsrst_delay 200
adapter_nsrst_assert_width 200

# Set flash parameters
set FLASH_BASE 0x10000000
set FLASH_SIZE 0x80000
set FLC_BASE 0x40029000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
set FLASH_OPTIONS 0x01

# Use Serial Wire Debug
transport select swd

source [find target/max32xxx.cfg]

# Add additional flash bank
set FLASH_BASE 0x10080000
set FLC_BASE 0x40029400

flash bank $_CHIPNAME.flash1 max32xxx $FLASH_BASE $FLASH_SIZE 0 0 $_CHIPNAME.cpu \
$FLC_BASE $FLASH_SECTOR $FLASH_CLK $FLASH_OPTIONS