# SPDX-License-Identifier: GPL-2.0-or-later
# Maxim Integrated MAX32690 - Arm Cortex-M4F @ 120MHz

# Set the reset pin configuration
reset_config srst_only
adapter srst pulse_width 2

# Set flash parameters
set FLASH_BASE 0x10000000
set FLASH_SIZE 0x300000
set FLC_BASE 0x40029000
set FLASH_SECTOR 0x4000
set FLASH_CLK 60
set FLASH_OPTIONS 0x01

# Use Serial Wire Debug
transport select swd

source [find target/max32xxx_common.cfg]

# Add additional flash bank
set FLASH_BASE 0x10300000
set FLASH_SIZE 0x40000
set FLC_BASE 0x40029400
set FLASH_SECTOR 0x2000

flash bank $_CHIPNAME.flash1 max32xxx $FLASH_BASE $FLASH_SIZE 0 0 $_CHIPNAME.cpu \
$FLC_BASE $FLASH_SECTOR $FLASH_CLK $FLASH_OPTIONS

# Early revisions of the MAX32690 will disable SWD upon reset. There are reserved address locations
# in the ROM code that can be used to insert breakpoints.
# This workaround will enable SWD for affected revisions.
$_CHIPNAME.cpu configure -event reset-assert-pre {
   if {$halt} {
      catch {bp 0x0000FFF4 2 hw}
   }
}

$_CHIPNAME.cpu configure -event reset-deassert-post {
   if {$halt} {
      $::_CHIPNAME.cpu arp_poll
      $::_CHIPNAME.cpu arp_poll
      $::_CHIPNAME.cpu arp_halt
      rbp 0x0000FFF4
   }
}