0baecf9943
According to AM4379 TRM [1], table 2-1 L3 Memory Map, we have a total of 256KiB and there's no reason not to use it all. [1] http://www.ti.com/lit/ug/spruhl7b/spruhl7b.pdf Change-Id: I117f2afe721bc4e3f0df304d3542e1a91aa69d12 Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-on: http://openocd.zylin.com/2611 Tested-by: jenkins Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
52 lines
1.4 KiB
INI
52 lines
1.4 KiB
INI
source [find target/icepick.cfg]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME am437x
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}
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#
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# M3 DAP
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#
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if { [info exists M3_DAP_TAPID] } {
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set _M3_DAP_TAPID $M3_DAP_TAPID
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} else {
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set _M3_DAP_TAPID 0x4b6b902f
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}
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jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
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jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11"
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#
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# Cortex A9 DAP
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#
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x4b6b902f
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}
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
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jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12"
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#
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# ICEpick-D (JTAG route controller)
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#
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if { [info exists JRC_TAPID] } {
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set _JRC_TAPID $JRC_TAPID
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} else {
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set _JRC_TAPID 0x0b98c02f
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
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jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
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# some TCK tycles are required to activate the DEBUG power domain
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jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
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#
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# Cortex A9 target
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#
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80000000
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# SRAM: 256K at 0x4030.0000
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$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x40000
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