16e17ab1b3
Some cleanup of the ARMv7-M support:
- Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and
update the Cortex-M3 doc refs (DDI 0337C is no longer available).
- Those registers aren't actually general, and some are incorrect (per all
public docs anyway). Update comments and code accordingly.
* What the Core Debug facility exposes is *implementation-specific*
not architectural. These values aren't fully portable. They match
Cortex-M3 ... so no current implementation will make trouble, but
the next v7m implementation might.
* Four of the registers are actually not exposed that way. Before
Cortex-M3 r2p0 they are read/written through MRS/MSR instructions.
In that newest silicon, they are four bytes in one register, not
four separate registers.
- Update the CM3 code to report when that one register is available,
and not try to access it when it isn't. Also declare the register
numbers that an eventual MRS/MSR solution will need to be using.
- Stop line wrapping the exception labels.
So for parts before r2p0 OpenOCD behavior is effectively unchanged, and
still buggy; but for those newer parts a few things might now be correct.
Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include
most LM3S parts and all STM32 parts. Parts using r2p0 are available, and
include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx
parts which are now sampling.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
210 lines
7.2 KiB
C
210 lines
7.2 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef CORTEX_M3_H
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#define CORTEX_M3_H
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#include "register.h"
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#include "target.h"
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#include "armv7m.h"
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//#include "arm_adi_v5.h"
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extern char* cortex_m3_state_strings[];
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#define CORTEX_M3_COMMON_MAGIC 0x1A451A45
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#define SYSTEM_CONTROL_BASE 0x400FE000
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#define CPUID 0xE000ED00
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/* Debug Control Block */
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#define DCB_DHCSR 0xE000EDF0
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#define DCB_DCRSR 0xE000EDF4
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#define DCB_DCRDR 0xE000EDF8
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#define DCB_DEMCR 0xE000EDFC
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#define DCRSR_WnR (1 << 16)
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#define DWT_CTRL 0xE0001000
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#define DWT_COMP0 0xE0001020
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#define DWT_MASK0 0xE0001024
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#define DWT_FUNCTION0 0xE0001028
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#define FP_CTRL 0xE0002000
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#define FP_REMAP 0xE0002004
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#define FP_COMP0 0xE0002008
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#define FP_COMP1 0xE000200C
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#define FP_COMP2 0xE0002010
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#define FP_COMP3 0xE0002014
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#define FP_COMP4 0xE0002018
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#define FP_COMP5 0xE000201C
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#define FP_COMP6 0xE0002020
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#define FP_COMP7 0xE0002024
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#define DWT_CTRL 0xE0001000
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/* DCB_DHCSR bit and field definitions */
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#define DBGKEY (0xA05F << 16)
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#define C_DEBUGEN (1 << 0)
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#define C_HALT (1 << 1)
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#define C_STEP (1 << 2)
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#define C_MASKINTS (1 << 3)
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#define S_REGRDY (1 << 16)
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#define S_HALT (1 << 17)
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#define S_SLEEP (1 << 18)
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#define S_LOCKUP (1 << 19)
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#define S_RETIRE_ST (1 << 24)
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#define S_RESET_ST (1 << 25)
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/* DCB_DEMCR bit and field definitions */
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#define TRCENA (1 << 24)
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#define VC_HARDERR (1 << 10)
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#define VC_BUSERR (1 << 8)
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#define VC_CORERESET (1 << 0)
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#define NVIC_ICTR 0xE000E004
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#define NVIC_ISE0 0xE000E100
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#define NVIC_ICSR 0xE000ED04
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#define NVIC_AIRCR 0xE000ED0C
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#define NVIC_SHCSR 0xE000ED24
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#define NVIC_CFSR 0xE000ED28
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#define NVIC_MMFSRb 0xE000ED28
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#define NVIC_BFSRb 0xE000ED29
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#define NVIC_USFSRh 0xE000ED2A
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#define NVIC_HFSR 0xE000ED2C
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#define NVIC_DFSR 0xE000ED30
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#define NVIC_MMFAR 0xE000ED34
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#define NVIC_BFAR 0xE000ED38
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/* NVIC_AIRCR bits */
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#define AIRCR_VECTKEY (0x5FA << 16)
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#define AIRCR_SYSRESETREQ (1 << 2)
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#define AIRCR_VECTCLRACTIVE (1 << 1)
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#define AIRCR_VECTRESET (1 << 0)
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/* NVIC_SHCSR bits */
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#define SHCSR_BUSFAULTENA (1 << 17)
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/* NVIC_DFSR bits */
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#define DFSR_HALTED 1
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#define DFSR_BKPT 2
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#define DFSR_DWTTRAP 4
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#define DFSR_VCATCH 8
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#define FPCR_CODE 0
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#define FPCR_LITERAL 1
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#define FPCR_REPLACE_REMAP (0 << 30)
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#define FPCR_REPLACE_BKPT_LOW (1 << 30)
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#define FPCR_REPLACE_BKPT_HIGH (2 << 30)
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#define FPCR_REPLACE_BKPT_BOTH (3 << 30)
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/* Use MRS/MSR to read/write any of these special registers. Some of
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* them (xPSR, MSP, PSP) are always available using DCRxR. Starting in
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* Cortex-M3 r2p0, some (CONTROL, BASEPRI, and *MASK) are also available
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* through DCRxR.
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* NOTE: this listing omits xPSR components and other mixtures.
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*/
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#define SR_XPSR 3
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#define SR_MSP 8
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#define SR_PSP 9
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#define SR_PRIMASK 16
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#define SR_BASEPRI 17
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#define SR_BASEPRI_MAX 18
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#define SR_FAULTMASK 19
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#define SR_CONTROL 20
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typedef struct cortex_m3_fp_comparator_s
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{
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int used;
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int type;
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uint32_t fpcr_value;
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uint32_t fpcr_address;
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} cortex_m3_fp_comparator_t;
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typedef struct cortex_m3_dwt_comparator_s
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{
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int used;
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uint32_t comp;
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uint32_t mask;
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uint32_t function;
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uint32_t dwt_comparator_address;
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} cortex_m3_dwt_comparator_t;
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typedef struct cortex_m3_common_s
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{
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int common_magic;
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arm_jtag_t jtag_info;
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/* Context information */
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uint32_t dcb_dhcsr;
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uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
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uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
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/* Flash Patch and Breakpoint (FPB) */
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int fp_num_lit;
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int fp_num_code;
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int fp_code_available;
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int fpb_enabled;
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int auto_bp_type;
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cortex_m3_fp_comparator_t *fp_comparator_list;
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/* Data Watchpoint and Trace (DWT) */
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int dwt_num_comp;
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int dwt_comp_available;
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cortex_m3_dwt_comparator_t *dwt_comparator_list;
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/* Interrupts */
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int intlinesnum;
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uint32_t *intsetenable;
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armv7m_common_t armv7m;
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// swjdp_common_t swjdp_info;
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void *arch_info;
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} cortex_m3_common_t;
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extern void cortex_m3_build_reg_cache(target_t *target);
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int cortex_m3_poll(target_t *target);
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int cortex_m3_halt(target_t *target);
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int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
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int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
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int cortex_m3_assert_reset(target_t *target);
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int cortex_m3_deassert_reset(target_t *target);
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int cortex_m3_soft_reset_halt(struct target_s *target);
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int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer);
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int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
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int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
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int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
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int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
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int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
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int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
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//extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
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extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap);
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#endif /* CORTEX_M3_H */
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