We don't want an ARMv7-specific core state enumeration just to add ThumbEE state. Update the generic stuff to handle that, and replace the V7-specific bits with it. For Cortex-A8: on debug entry, check both the T and J bits instead of just the T bit. When the J bit is set, set the right state and warn appropriately. (And while we're at it, move the generic arm struct to the front of the v7a structure, for somewhat better code generation.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
1153 lines
32 KiB
C
1153 lines
32 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by Oyvind Harboe *
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* oyvind.harboe@zylin.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "armv4_5.h"
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#include "arm_jtag.h"
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#include "breakpoints.h"
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#include "arm_disassembler.h"
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#include "binarybuffer.h"
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#include "algorithm.h"
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#include "register.h"
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static const char *armv4_5_core_reg_list[] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "sp_usr", "lr_usr", "pc",
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"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", "lr_fiq",
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"sp_irq", "lr_irq",
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"sp_svc", "lr_svc",
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"sp_abt", "lr_abt",
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"sp_und", "lr_und",
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"cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und",
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"sp_mon", "lr_mon", "spsr_mon",
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};
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static const uint8_t arm_usr_indices[17] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
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};
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static const uint8_t arm_fiq_indices[8] = {
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16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
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};
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static const uint8_t arm_irq_indices[3] = {
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23, 24, ARMV4_5_SPSR_IRQ,
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};
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static const uint8_t arm_svc_indices[3] = {
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25, 26, ARMV4_5_SPSR_SVC,
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};
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static const uint8_t arm_abt_indices[3] = {
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27, 28, ARMV4_5_SPSR_ABT,
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};
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static const uint8_t arm_und_indices[3] = {
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29, 30, ARMV4_5_SPSR_UND,
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};
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static const uint8_t arm_mon_indices[3] = {
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37, 38, ARM_SPSR_MON,
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};
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static const struct {
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const char *name;
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unsigned short psr;
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/* For user and system modes, these list indices for all registers.
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* otherwise they're just indices for the shadow registers and SPSR.
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*/
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unsigned short n_indices;
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const uint8_t *indices;
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} arm_mode_data[] = {
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/* Seven modes are standard from ARM7 on. "System" and "User" share
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* the same registers; other modes shadow from 3 to 8 registers.
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*/
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{
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.name = "User",
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.psr = ARMV4_5_MODE_USR,
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.n_indices = ARRAY_SIZE(arm_usr_indices),
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.indices = arm_usr_indices,
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},
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{
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.name = "FIQ",
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.psr = ARMV4_5_MODE_FIQ,
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.n_indices = ARRAY_SIZE(arm_fiq_indices),
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.indices = arm_fiq_indices,
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},
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{
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.name = "Supervisor",
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.psr = ARMV4_5_MODE_SVC,
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.n_indices = ARRAY_SIZE(arm_svc_indices),
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.indices = arm_svc_indices,
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},
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{
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.name = "Abort",
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.psr = ARMV4_5_MODE_ABT,
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.n_indices = ARRAY_SIZE(arm_abt_indices),
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.indices = arm_abt_indices,
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},
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{
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.name = "IRQ",
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.psr = ARMV4_5_MODE_IRQ,
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.n_indices = ARRAY_SIZE(arm_irq_indices),
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.indices = arm_irq_indices,
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},
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{
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.name = "Undefined instruction",
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.psr = ARMV4_5_MODE_UND,
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.n_indices = ARRAY_SIZE(arm_und_indices),
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.indices = arm_und_indices,
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},
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{
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.name = "System",
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.psr = ARMV4_5_MODE_SYS,
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.n_indices = ARRAY_SIZE(arm_usr_indices),
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.indices = arm_usr_indices,
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},
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/* TrustZone "Security Extensions" add a secure monitor mode.
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* This is distinct from a "debug monitor" which can support
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* non-halting debug, in conjunction with some debuggers.
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*/
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{
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.name = "Secure Monitor",
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.psr = ARM_MODE_MON,
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.n_indices = ARRAY_SIZE(arm_mon_indices),
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.indices = arm_mon_indices,
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},
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};
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/** Map PSR mode bits to the name of an ARM processor operating mode. */
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const char *arm_mode_name(unsigned psr_mode)
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{
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for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
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if (arm_mode_data[i].psr == psr_mode)
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return arm_mode_data[i].name;
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}
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LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
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return "UNRECOGNIZED";
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}
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/** Return true iff the parameter denotes a valid ARM processor mode. */
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bool is_arm_mode(unsigned psr_mode)
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{
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for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
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if (arm_mode_data[i].psr == psr_mode)
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return true;
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}
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return false;
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}
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/** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
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int armv4_5_mode_to_number(enum armv4_5_mode mode)
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{
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switch (mode) {
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case ARMV4_5_MODE_ANY:
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/* map MODE_ANY to user mode */
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case ARMV4_5_MODE_USR:
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return 0;
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case ARMV4_5_MODE_FIQ:
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return 1;
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case ARMV4_5_MODE_IRQ:
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return 2;
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case ARMV4_5_MODE_SVC:
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return 3;
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case ARMV4_5_MODE_ABT:
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return 4;
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case ARMV4_5_MODE_UND:
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return 5;
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case ARMV4_5_MODE_SYS:
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return 6;
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case ARM_MODE_MON:
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return 7;
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default:
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LOG_ERROR("invalid mode value encountered %d", mode);
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return -1;
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}
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}
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/** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
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enum armv4_5_mode armv4_5_number_to_mode(int number)
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{
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switch (number) {
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case 0:
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return ARMV4_5_MODE_USR;
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case 1:
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return ARMV4_5_MODE_FIQ;
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case 2:
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return ARMV4_5_MODE_IRQ;
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case 3:
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return ARMV4_5_MODE_SVC;
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case 4:
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return ARMV4_5_MODE_ABT;
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case 5:
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return ARMV4_5_MODE_UND;
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case 6:
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return ARMV4_5_MODE_SYS;
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case 7:
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return ARM_MODE_MON;
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default:
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LOG_ERROR("mode index out of bounds %d", number);
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return ARMV4_5_MODE_ANY;
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}
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}
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char* armv4_5_state_strings[] =
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{
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"ARM", "Thumb", "Jazelle", "ThumbEE",
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};
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static const struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
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{
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{0, ARMV4_5_MODE_ANY, NULL, NULL},
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{1, ARMV4_5_MODE_ANY, NULL, NULL},
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{2, ARMV4_5_MODE_ANY, NULL, NULL},
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{3, ARMV4_5_MODE_ANY, NULL, NULL},
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{4, ARMV4_5_MODE_ANY, NULL, NULL},
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{5, ARMV4_5_MODE_ANY, NULL, NULL},
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{6, ARMV4_5_MODE_ANY, NULL, NULL},
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{7, ARMV4_5_MODE_ANY, NULL, NULL},
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{8, ARMV4_5_MODE_ANY, NULL, NULL},
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{9, ARMV4_5_MODE_ANY, NULL, NULL},
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{10, ARMV4_5_MODE_ANY, NULL, NULL},
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{11, ARMV4_5_MODE_ANY, NULL, NULL},
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{12, ARMV4_5_MODE_ANY, NULL, NULL},
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{13, ARMV4_5_MODE_USR, NULL, NULL},
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{14, ARMV4_5_MODE_USR, NULL, NULL},
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{15, ARMV4_5_MODE_ANY, NULL, NULL},
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{8, ARMV4_5_MODE_FIQ, NULL, NULL},
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{9, ARMV4_5_MODE_FIQ, NULL, NULL},
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{10, ARMV4_5_MODE_FIQ, NULL, NULL},
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{11, ARMV4_5_MODE_FIQ, NULL, NULL},
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{12, ARMV4_5_MODE_FIQ, NULL, NULL},
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{13, ARMV4_5_MODE_FIQ, NULL, NULL},
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{14, ARMV4_5_MODE_FIQ, NULL, NULL},
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{13, ARMV4_5_MODE_IRQ, NULL, NULL},
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{14, ARMV4_5_MODE_IRQ, NULL, NULL},
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{13, ARMV4_5_MODE_SVC, NULL, NULL},
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{14, ARMV4_5_MODE_SVC, NULL, NULL},
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{13, ARMV4_5_MODE_ABT, NULL, NULL},
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{14, ARMV4_5_MODE_ABT, NULL, NULL},
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{13, ARMV4_5_MODE_UND, NULL, NULL},
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{14, ARMV4_5_MODE_UND, NULL, NULL},
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{16, ARMV4_5_MODE_ANY, NULL, NULL},
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{16, ARMV4_5_MODE_FIQ, NULL, NULL},
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{16, ARMV4_5_MODE_IRQ, NULL, NULL},
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{16, ARMV4_5_MODE_SVC, NULL, NULL},
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{16, ARMV4_5_MODE_ABT, NULL, NULL},
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{16, ARMV4_5_MODE_UND, NULL, NULL},
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{13, ARM_MODE_MON, NULL, NULL},
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{14, ARM_MODE_MON, NULL, NULL},
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{16, ARM_MODE_MON, NULL, NULL},
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};
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/* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
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const int armv4_5_core_reg_map[8][17] =
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{
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{ /* USR */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
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},
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{ /* FIQ (8 shadows of USR, vs normal 3) */
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0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
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},
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{ /* IRQ */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
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},
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{ /* SVC */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
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},
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{ /* ABT */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
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},
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{ /* UND */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
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},
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{ /* SYS (same registers as USR) */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
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},
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{ /* MON */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
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}
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};
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static const uint8_t arm_gdb_dummy_fp_value[12];
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/**
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* Dummy FPA registers are required to support GDB on ARM.
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* Register packets require eight obsolete FPA register values.
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* Modern ARM cores use Vector Floating Point (VFP), if they
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* have any floating point support. VFP is not FPA-compatible.
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*/
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struct reg arm_gdb_dummy_fp_reg =
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{
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.name = "GDB dummy FPA register",
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.value = (uint8_t *) arm_gdb_dummy_fp_value,
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.valid = 1,
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.size = 96,
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};
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static const uint8_t arm_gdb_dummy_fps_value[4];
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|
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/**
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* Dummy FPA status registers are required to support GDB on ARM.
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* Register packets require an obsolete FPA status register.
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*/
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struct reg arm_gdb_dummy_fps_reg =
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{
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.name = "GDB dummy FPA status register",
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.value = (uint8_t *) arm_gdb_dummy_fps_value,
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.valid = 1,
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.size = 32,
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};
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static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
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static void arm_gdb_dummy_init(void)
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{
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register_init_dummy(&arm_gdb_dummy_fp_reg);
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register_init_dummy(&arm_gdb_dummy_fps_reg);
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}
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|
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static int armv4_5_get_core_reg(struct reg *reg)
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{
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int retval;
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struct armv4_5_core_reg *armv4_5 = reg->arch_info;
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struct target *target = armv4_5->target;
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if (target->state != TARGET_HALTED)
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{
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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|
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retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode);
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if (retval == ERROR_OK)
|
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reg->valid = 1;
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|
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return retval;
|
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}
|
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|
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static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
|
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{
|
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struct armv4_5_core_reg *armv4_5 = reg->arch_info;
|
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struct target *target = armv4_5->target;
|
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struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target);
|
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uint32_t value = buf_get_u32(buf, 0, 32);
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|
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if (target->state != TARGET_HALTED)
|
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{
|
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LOG_ERROR("Target not halted");
|
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return ERROR_TARGET_NOT_HALTED;
|
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}
|
|
|
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if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR])
|
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{
|
|
if (value & 0x20)
|
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{
|
|
/* T bit should be set */
|
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if (armv4_5_target->core_state == ARMV4_5_STATE_ARM)
|
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{
|
|
/* change state to Thumb */
|
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LOG_DEBUG("changing to Thumb state");
|
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armv4_5_target->core_state = ARMV4_5_STATE_THUMB;
|
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}
|
|
}
|
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else
|
|
{
|
|
/* T bit should be cleared */
|
|
if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB)
|
|
{
|
|
/* change state to ARM */
|
|
LOG_DEBUG("changing to ARM state");
|
|
armv4_5_target->core_state = ARMV4_5_STATE_ARM;
|
|
}
|
|
}
|
|
|
|
if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f))
|
|
{
|
|
LOG_DEBUG("changing ARM core mode to '%s'",
|
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arm_mode_name(value & 0x1f));
|
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armv4_5_target->core_mode = value & 0x1f;
|
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armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value);
|
|
}
|
|
}
|
|
|
|
buf_set_u32(reg->value, 0, 32, value);
|
|
reg->dirty = 1;
|
|
reg->valid = 1;
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static const struct reg_arch_type arm_reg_type = {
|
|
.get = armv4_5_get_core_reg,
|
|
.set = armv4_5_set_core_reg,
|
|
};
|
|
|
|
/** Marks the contents of the register cache as invalid (and clean). */
|
|
int armv4_5_invalidate_core_regs(struct target *target)
|
|
{
|
|
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
|
|
unsigned num_regs = armv4_5->core_cache->num_regs;
|
|
struct reg *reg = armv4_5->core_cache->reg_list;
|
|
|
|
for (unsigned i = 0; i < num_regs; i++, reg++) {
|
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reg->valid = 0;
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reg->dirty = 0;
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|
}
|
|
|
|
/* FIXME don't bother returning a value then */
|
|
return ERROR_OK;
|
|
}
|
|
|
|
struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
|
|
{
|
|
int num_regs = ARRAY_SIZE(armv4_5_core_reg_list_arch_info);
|
|
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
|
|
struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
|
|
struct armv4_5_core_reg *arch_info = calloc(num_regs,
|
|
sizeof(struct armv4_5_core_reg));
|
|
int i;
|
|
|
|
if (!cache || !reg_list || !arch_info) {
|
|
free(cache);
|
|
free(reg_list);
|
|
free(arch_info);
|
|
return NULL;
|
|
}
|
|
|
|
cache->name = "ARM registers";
|
|
cache->next = NULL;
|
|
cache->reg_list = reg_list;
|
|
cache->num_regs = 0;
|
|
|
|
for (i = 0; i < num_regs; i++)
|
|
{
|
|
/* Skip registers this core doesn't expose */
|
|
if (armv4_5_core_reg_list_arch_info[i].mode == ARM_MODE_MON
|
|
&& armv4_5_common->core_type != ARM_MODE_MON)
|
|
continue;
|
|
|
|
/* REVISIT handle Cortex-M, which only shadows R13/SP */
|
|
|
|
arch_info[i] = armv4_5_core_reg_list_arch_info[i];
|
|
arch_info[i].target = target;
|
|
arch_info[i].armv4_5_common = armv4_5_common;
|
|
reg_list[i].name = (char *) armv4_5_core_reg_list[i];
|
|
reg_list[i].size = 32;
|
|
reg_list[i].value = calloc(1, 4);
|
|
reg_list[i].type = &arm_reg_type;
|
|
reg_list[i].arch_info = &arch_info[i];
|
|
|
|
cache->num_regs++;
|
|
}
|
|
|
|
return cache;
|
|
}
|
|
|
|
int armv4_5_arch_state(struct target *target)
|
|
{
|
|
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
|
|
|
|
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
|
|
{
|
|
LOG_ERROR("BUG: called for a non-ARMv4/5 target");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
|
|
armv4_5_state_strings[armv4_5->core_state],
|
|
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
|
|
arm_mode_name(armv4_5->core_mode),
|
|
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
|
|
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
|
|
cache->reg_list[armv4_5_core_reg_map[mode][num]]
|
|
|
|
COMMAND_HANDLER(handle_armv4_5_reg_command)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
|
|
unsigned num_regs;
|
|
struct reg *regs;
|
|
|
|
if (!is_arm(armv4_5))
|
|
{
|
|
command_print(CMD_CTX, "current target isn't an ARM");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
if (target->state != TARGET_HALTED)
|
|
{
|
|
command_print(CMD_CTX, "error: target must be halted for register accesses");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
if (!is_arm_mode(armv4_5->core_mode))
|
|
return ERROR_FAIL;
|
|
|
|
if (!armv4_5->full_context) {
|
|
command_print(CMD_CTX, "error: target doesn't support %s",
|
|
CMD_NAME);
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
num_regs = armv4_5->core_cache->num_regs;
|
|
regs = armv4_5->core_cache->reg_list;
|
|
|
|
for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
|
|
const char *name;
|
|
char *sep = "\n";
|
|
char *shadow = "";
|
|
|
|
/* label this bank of registers (or shadows) */
|
|
switch (arm_mode_data[mode].psr) {
|
|
case ARMV4_5_MODE_SYS:
|
|
continue;
|
|
case ARMV4_5_MODE_USR:
|
|
name = "System and User";
|
|
sep = "";
|
|
break;
|
|
case ARM_MODE_MON:
|
|
if (armv4_5->core_type != ARM_MODE_MON)
|
|
continue;
|
|
/* FALLTHROUGH */
|
|
default:
|
|
name = arm_mode_data[mode].name;
|
|
shadow = "shadow ";
|
|
break;
|
|
}
|
|
command_print(CMD_CTX, "%s%s mode %sregisters",
|
|
sep, name, shadow);
|
|
|
|
/* display N rows of up to 4 registers each */
|
|
for (unsigned i = 0; i < arm_mode_data[mode].n_indices;) {
|
|
char output[80];
|
|
int output_len = 0;
|
|
|
|
for (unsigned j = 0; j < 4; j++, i++) {
|
|
uint32_t value;
|
|
struct reg *reg = regs;
|
|
|
|
if (i >= arm_mode_data[mode].n_indices)
|
|
break;
|
|
|
|
reg += arm_mode_data[mode].indices[i];
|
|
|
|
/* REVISIT be smarter about faults... */
|
|
if (!reg->valid)
|
|
armv4_5->full_context(target);
|
|
|
|
value = buf_get_u32(reg->value, 0, 32);
|
|
output_len += snprintf(output + output_len,
|
|
sizeof(output) - output_len,
|
|
"%8s: %8.8" PRIx32 " ",
|
|
reg->name, value);
|
|
}
|
|
command_print(CMD_CTX, "%s", output);
|
|
}
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(handle_armv4_5_core_state_command)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
|
|
|
|
if (!is_arm(armv4_5))
|
|
{
|
|
command_print(CMD_CTX, "current target isn't an ARM");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
if (CMD_ARGC > 0)
|
|
{
|
|
if (strcmp(CMD_ARGV[0], "arm") == 0)
|
|
{
|
|
armv4_5->core_state = ARMV4_5_STATE_ARM;
|
|
}
|
|
if (strcmp(CMD_ARGV[0], "thumb") == 0)
|
|
{
|
|
armv4_5->core_state = ARMV4_5_STATE_THUMB;
|
|
}
|
|
}
|
|
|
|
command_print(CMD_CTX, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(handle_armv4_5_disassemble_command)
|
|
{
|
|
int retval = ERROR_OK;
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct arm *arm = target ? target_to_arm(target) : NULL;
|
|
uint32_t address;
|
|
int count = 1;
|
|
int thumb = 0;
|
|
|
|
if (!is_arm(arm)) {
|
|
command_print(CMD_CTX, "current target isn't an ARM");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
switch (CMD_ARGC) {
|
|
case 3:
|
|
if (strcmp(CMD_ARGV[2], "thumb") != 0)
|
|
goto usage;
|
|
thumb = 1;
|
|
/* FALL THROUGH */
|
|
case 2:
|
|
COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
|
|
/* FALL THROUGH */
|
|
case 1:
|
|
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
|
|
if (address & 0x01) {
|
|
if (!thumb) {
|
|
command_print(CMD_CTX, "Disassemble as Thumb");
|
|
thumb = 1;
|
|
}
|
|
address &= ~1;
|
|
}
|
|
break;
|
|
default:
|
|
usage:
|
|
command_print(CMD_CTX,
|
|
"usage: arm disassemble <address> [<count> ['thumb']]");
|
|
count = 0;
|
|
retval = ERROR_FAIL;
|
|
}
|
|
|
|
while (count-- > 0) {
|
|
struct arm_instruction cur_instruction;
|
|
|
|
if (thumb) {
|
|
/* Always use Thumb2 disassembly for best handling
|
|
* of 32-bit BL/BLX, and to work with newer cores
|
|
* (some ARMv6, all ARMv7) that use Thumb2.
|
|
*/
|
|
retval = thumb2_opcode(target, address,
|
|
&cur_instruction);
|
|
if (retval != ERROR_OK)
|
|
break;
|
|
} else {
|
|
uint32_t opcode;
|
|
|
|
retval = target_read_u32(target, address, &opcode);
|
|
if (retval != ERROR_OK)
|
|
break;
|
|
retval = arm_evaluate_opcode(opcode, address,
|
|
&cur_instruction) != ERROR_OK;
|
|
if (retval != ERROR_OK)
|
|
break;
|
|
}
|
|
command_print(CMD_CTX, "%s", cur_instruction.text);
|
|
address += cur_instruction.instruction_size;
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
int armv4_5_register_commands(struct command_context *cmd_ctx)
|
|
{
|
|
struct command *armv4_5_cmd;
|
|
|
|
armv4_5_cmd = register_command(cmd_ctx, NULL, "arm",
|
|
NULL, COMMAND_ANY,
|
|
"generic ARM commands");
|
|
|
|
register_command(cmd_ctx, armv4_5_cmd, "reg",
|
|
handle_armv4_5_reg_command, COMMAND_EXEC,
|
|
"display ARM core registers");
|
|
register_command(cmd_ctx, armv4_5_cmd, "core_state",
|
|
handle_armv4_5_core_state_command, COMMAND_EXEC,
|
|
"display/change ARM core state <arm | thumb>");
|
|
register_command(cmd_ctx, armv4_5_cmd, "disassemble",
|
|
handle_armv4_5_disassemble_command, COMMAND_EXEC,
|
|
"disassemble instructions "
|
|
"<address> [<count> ['thumb']]");
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
|
|
{
|
|
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
|
|
int i;
|
|
|
|
if (!is_arm_mode(armv4_5->core_mode))
|
|
return ERROR_FAIL;
|
|
|
|
*reg_list_size = 26;
|
|
*reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
|
|
|
|
for (i = 0; i < 16; i++)
|
|
{
|
|
(*reg_list)[i] = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i);
|
|
}
|
|
|
|
for (i = 16; i < 24; i++)
|
|
{
|
|
(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
|
|
}
|
|
|
|
(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
|
|
(*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR];
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
/* wait for execution to complete and check exit point */
|
|
static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
|
|
{
|
|
int retval;
|
|
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
|
|
|
|
if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
if (target->state != TARGET_HALTED)
|
|
{
|
|
if ((retval = target_halt(target)) != ERROR_OK)
|
|
return retval;
|
|
if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
return ERROR_TARGET_TIMEOUT;
|
|
}
|
|
|
|
/* fast exit: ARMv5+ code can use BKPT */
|
|
if (exit_point && buf_get_u32(armv4_5->core_cache->reg_list[15].value,
|
|
0, 32) != exit_point)
|
|
{
|
|
LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
|
|
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
|
|
return ERROR_TARGET_TIMEOUT;
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info))
|
|
{
|
|
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
|
|
struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
|
|
enum armv4_5_state core_state = armv4_5->core_state;
|
|
enum armv4_5_mode core_mode = armv4_5->core_mode;
|
|
uint32_t context[17];
|
|
uint32_t cpsr;
|
|
int exit_breakpoint_size = 0;
|
|
int i;
|
|
int retval = ERROR_OK;
|
|
LOG_DEBUG("Running algorithm");
|
|
|
|
if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
|
|
{
|
|
LOG_ERROR("current target isn't an ARMV4/5 target");
|
|
return ERROR_TARGET_INVALID;
|
|
}
|
|
|
|
if (target->state != TARGET_HALTED)
|
|
{
|
|
LOG_WARNING("target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
if (!is_arm_mode(armv4_5->core_mode))
|
|
return ERROR_FAIL;
|
|
|
|
/* armv5 and later can terminate with BKPT instruction; less overhead */
|
|
if (!exit_point && armv4_5->is_armv4)
|
|
{
|
|
LOG_ERROR("ARMv4 target needs HW breakpoint location");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
for (i = 0; i <= 16; i++)
|
|
{
|
|
if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid)
|
|
armv4_5->read_core_reg(target, i, armv4_5_algorithm_info->core_mode);
|
|
context[i] = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
|
|
}
|
|
cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32);
|
|
|
|
for (i = 0; i < num_mem_params; i++)
|
|
{
|
|
if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < num_reg_params; i++)
|
|
{
|
|
struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
|
|
if (!reg)
|
|
{
|
|
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
|
|
return ERROR_INVALID_ARGUMENTS;
|
|
}
|
|
|
|
if (reg->size != reg_params[i].size)
|
|
{
|
|
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
|
|
return ERROR_INVALID_ARGUMENTS;
|
|
}
|
|
|
|
if ((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
}
|
|
|
|
armv4_5->core_state = armv4_5_algorithm_info->core_state;
|
|
if (armv4_5->core_state == ARMV4_5_STATE_ARM)
|
|
exit_breakpoint_size = 4;
|
|
else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
|
|
exit_breakpoint_size = 2;
|
|
else
|
|
{
|
|
LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
|
|
return ERROR_INVALID_ARGUMENTS;
|
|
}
|
|
|
|
if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
|
|
{
|
|
LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode);
|
|
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode);
|
|
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
|
|
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
|
|
}
|
|
|
|
/* terminate using a hardware or (ARMv5+) software breakpoint */
|
|
if (exit_point && (retval = breakpoint_add(target, exit_point,
|
|
exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
|
|
{
|
|
LOG_ERROR("can't add HW breakpoint to terminate algorithm");
|
|
return ERROR_TARGET_FAILURE;
|
|
}
|
|
|
|
if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
|
|
{
|
|
return retval;
|
|
}
|
|
int retvaltemp;
|
|
retval = run_it(target, exit_point, timeout_ms, arch_info);
|
|
|
|
if (exit_point)
|
|
breakpoint_remove(target, exit_point);
|
|
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
for (i = 0; i < num_mem_params; i++)
|
|
{
|
|
if (mem_params[i].direction != PARAM_OUT)
|
|
if ((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
|
|
{
|
|
retval = retvaltemp;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < num_reg_params; i++)
|
|
{
|
|
if (reg_params[i].direction != PARAM_OUT)
|
|
{
|
|
|
|
struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
|
|
if (!reg)
|
|
{
|
|
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
|
|
retval = ERROR_INVALID_ARGUMENTS;
|
|
continue;
|
|
}
|
|
|
|
if (reg->size != reg_params[i].size)
|
|
{
|
|
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
|
|
retval = ERROR_INVALID_ARGUMENTS;
|
|
continue;
|
|
}
|
|
|
|
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
|
|
}
|
|
}
|
|
|
|
for (i = 0; i <= 16; i++)
|
|
{
|
|
uint32_t regvalue;
|
|
regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
|
|
if (regvalue != context[i])
|
|
{
|
|
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
|
|
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
|
|
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
|
|
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
|
|
}
|
|
}
|
|
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
|
|
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
|
|
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
|
|
|
|
armv4_5->core_state = core_state;
|
|
armv4_5->core_mode = core_mode;
|
|
|
|
return retval;
|
|
}
|
|
|
|
int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
|
|
{
|
|
return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
|
|
}
|
|
|
|
/**
|
|
* Runs ARM code in the target to calculate a CRC32 checksum.
|
|
*
|
|
* \todo On ARMv5+, rely on BKPT termination for reduced overhead.
|
|
*/
|
|
int arm_checksum_memory(struct target *target,
|
|
uint32_t address, uint32_t count, uint32_t *checksum)
|
|
{
|
|
struct working_area *crc_algorithm;
|
|
struct armv4_5_algorithm armv4_5_info;
|
|
struct reg_param reg_params[2];
|
|
int retval;
|
|
uint32_t i;
|
|
|
|
static const uint32_t arm_crc_code[] = {
|
|
0xE1A02000, /* mov r2, r0 */
|
|
0xE3E00000, /* mov r0, #0xffffffff */
|
|
0xE1A03001, /* mov r3, r1 */
|
|
0xE3A04000, /* mov r4, #0 */
|
|
0xEA00000B, /* b ncomp */
|
|
/* nbyte: */
|
|
0xE7D21004, /* ldrb r1, [r2, r4] */
|
|
0xE59F7030, /* ldr r7, CRC32XOR */
|
|
0xE0200C01, /* eor r0, r0, r1, asl 24 */
|
|
0xE3A05000, /* mov r5, #0 */
|
|
/* loop: */
|
|
0xE3500000, /* cmp r0, #0 */
|
|
0xE1A06080, /* mov r6, r0, asl #1 */
|
|
0xE2855001, /* add r5, r5, #1 */
|
|
0xE1A00006, /* mov r0, r6 */
|
|
0xB0260007, /* eorlt r0, r6, r7 */
|
|
0xE3550008, /* cmp r5, #8 */
|
|
0x1AFFFFF8, /* bne loop */
|
|
0xE2844001, /* add r4, r4, #1 */
|
|
/* ncomp: */
|
|
0xE1540003, /* cmp r4, r3 */
|
|
0x1AFFFFF1, /* bne nbyte */
|
|
/* end: */
|
|
0xEAFFFFFE, /* b end */
|
|
/* CRC32XOR: */
|
|
0x04C11DB7 /* .word 0x04C11DB7 */
|
|
};
|
|
|
|
retval = target_alloc_working_area(target,
|
|
sizeof(arm_crc_code), &crc_algorithm);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
/* convert code into a buffer in target endianness */
|
|
for (i = 0; i < ARRAY_SIZE(arm_crc_code); i++) {
|
|
retval = target_write_u32(target,
|
|
crc_algorithm->address + i * sizeof(uint32_t),
|
|
arm_crc_code[i]);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
}
|
|
|
|
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
|
|
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
|
|
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
|
|
|
|
init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
|
|
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
|
|
|
|
buf_set_u32(reg_params[0].value, 0, 32, address);
|
|
buf_set_u32(reg_params[1].value, 0, 32, count);
|
|
|
|
/* 20 second timeout/megabyte */
|
|
int timeout = 20000 * (1 + (count / (1024 * 1024)));
|
|
|
|
retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
|
|
crc_algorithm->address,
|
|
crc_algorithm->address + sizeof(arm_crc_code) - 8,
|
|
timeout, &armv4_5_info);
|
|
if (retval != ERROR_OK) {
|
|
LOG_ERROR("error executing ARM crc algorithm");
|
|
destroy_reg_param(®_params[0]);
|
|
destroy_reg_param(®_params[1]);
|
|
target_free_working_area(target, crc_algorithm);
|
|
return retval;
|
|
}
|
|
|
|
*checksum = buf_get_u32(reg_params[0].value, 0, 32);
|
|
|
|
destroy_reg_param(®_params[0]);
|
|
destroy_reg_param(®_params[1]);
|
|
|
|
target_free_working_area(target, crc_algorithm);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
/**
|
|
* Runs ARM code in the target to check whether a memory block holds
|
|
* all ones. NOR flash which has been erased, and thus may be written,
|
|
* holds all ones.
|
|
*
|
|
* \todo On ARMv5+, rely on BKPT termination for reduced overhead.
|
|
*/
|
|
int arm_blank_check_memory(struct target *target,
|
|
uint32_t address, uint32_t count, uint32_t *blank)
|
|
{
|
|
struct working_area *check_algorithm;
|
|
struct reg_param reg_params[3];
|
|
struct armv4_5_algorithm armv4_5_info;
|
|
int retval;
|
|
uint32_t i;
|
|
|
|
static const uint32_t check_code[] = {
|
|
/* loop: */
|
|
0xe4d03001, /* ldrb r3, [r0], #1 */
|
|
0xe0022003, /* and r2, r2, r3 */
|
|
0xe2511001, /* subs r1, r1, #1 */
|
|
0x1afffffb, /* bne loop */
|
|
/* end: */
|
|
0xeafffffe /* b end */
|
|
};
|
|
|
|
/* make sure we have a working area */
|
|
retval = target_alloc_working_area(target,
|
|
sizeof(check_code), &check_algorithm);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
/* convert code into a buffer in target endianness */
|
|
for (i = 0; i < ARRAY_SIZE(check_code); i++) {
|
|
retval = target_write_u32(target,
|
|
check_algorithm->address
|
|
+ i * sizeof(uint32_t),
|
|
check_code[i]);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
}
|
|
|
|
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
|
|
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
|
|
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
|
|
|
|
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
|
|
buf_set_u32(reg_params[0].value, 0, 32, address);
|
|
|
|
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
|
|
buf_set_u32(reg_params[1].value, 0, 32, count);
|
|
|
|
init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
|
|
buf_set_u32(reg_params[2].value, 0, 32, 0xff);
|
|
|
|
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
|
|
check_algorithm->address,
|
|
check_algorithm->address + sizeof(check_code) - 4,
|
|
10000, &armv4_5_info);
|
|
if (retval != ERROR_OK) {
|
|
destroy_reg_param(®_params[0]);
|
|
destroy_reg_param(®_params[1]);
|
|
destroy_reg_param(®_params[2]);
|
|
target_free_working_area(target, check_algorithm);
|
|
return retval;
|
|
}
|
|
|
|
*blank = buf_get_u32(reg_params[2].value, 0, 32);
|
|
|
|
destroy_reg_param(®_params[0]);
|
|
destroy_reg_param(®_params[1]);
|
|
destroy_reg_param(®_params[2]);
|
|
|
|
target_free_working_area(target, check_algorithm);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int arm_full_context(struct target *target)
|
|
{
|
|
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
|
|
unsigned num_regs = armv4_5->core_cache->num_regs;
|
|
struct reg *reg = armv4_5->core_cache->reg_list;
|
|
int retval = ERROR_OK;
|
|
|
|
for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
|
|
if (reg->valid)
|
|
continue;
|
|
retval = armv4_5_get_core_reg(reg);
|
|
}
|
|
return retval;
|
|
}
|
|
|
|
int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
|
|
{
|
|
target->arch_info = armv4_5;
|
|
|
|
armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
|
|
armv4_5->core_state = ARMV4_5_STATE_ARM;
|
|
armv4_5->core_mode = ARMV4_5_MODE_USR;
|
|
|
|
/* core_type may be overridden by subtype logic */
|
|
armv4_5->core_type = ARMV4_5_MODE_ANY;
|
|
|
|
/* default full_context() has no core-specific optimizations */
|
|
if (!armv4_5->full_context && armv4_5->read_core_reg)
|
|
armv4_5->full_context = arm_full_context;
|
|
|
|
return ERROR_OK;
|
|
}
|