2053120ba1
ESP32-S3 is a dual core Xtensa SoC Not full featured yet. Some of the missing functionality: -Semihosting -Flash breakpoints -Flash loader -Apptrace -FreeRTOS Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: I44e17088030c96a9be9809f6579a4f16dbfc5794 Reviewed-on: https://review.openocd.org/c/openocd/+/6990 Tested-by: jenkins Reviewed-by: Ian Thompson <ianst@cadence.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
13 lines
318 B
Makefile
13 lines
318 B
Makefile
noinst_LTLIBRARIES += %D%/libespressif.la
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%C%_libespressif_la_SOURCES = \
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%D%/esp_xtensa.c \
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%D%/esp_xtensa.h \
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%D%/esp_xtensa_smp.c \
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%D%/esp_xtensa_smp.h \
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%D%/esp32.c \
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%D%/esp32.h \
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%D%/esp32s2.c \
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%D%/esp32s2.h \
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%D%/esp32s3.c \
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%D%/esp32s3.h
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