ceaa47a2aa
This new code implement two FIFOs for handling TX and RX JTAG data transfers, its simply receives data and send it OUT to target chip in respect of JTAG protocol timing constraints. The IN FIFO receives data from target chip and send it back to openocd. Change-Id: I17c1231e7f4b0a6b510359fe147b609922e0809e Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8715 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
23 lines
537 B
VHDL
23 lines
537 B
VHDL
library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.std_logic_arith.ALL;
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use ieee.std_logic_unsigned.ALL;
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entity DFF is
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port ( clk : in std_logic;
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reset : in std_logic;
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d : in std_logic;
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q : out std_logic);
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end DFF;
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architecture Behavioral of DFF is
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begin
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process(clk, reset)
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begin
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if reset = '1' then
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q <= '1'; -- Reset output to 0
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elsif rising_edge(clk) then
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q <= d; -- Capture D at the rising edge of the clock
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end if;
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end process;
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end Behavioral; |