c3ec1940b5
L0 is cortex m0+, so different id codes, SWD only, different addresses for the clock speedup. It has no endian options, no boundary scan. Removed all L0 specific portions from L1 files, and renamed files to clarify their purpose. The deprecated stm32lx_stlink.cfg is kept as is, as it is only around for backwards compatibility with prior releases. Tested on STM32L053 Discovery and STM32L151 Discovery. Has _not_ been tested with jtag on L1. Change-Id: I8eea890d2f92a302d9e9c8a8832d218ee1b6bcfc Signed-off-by: Karl Palsson <karlp@tweak.net.au> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2405 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Juha Niskanen <juha.niskanen@haltian.com>
109 lines
2.5 KiB
INI
109 lines
2.5 KiB
INI
#
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# stm32l1 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32l
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 10kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x2800
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}
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# JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
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adapter_khz 300
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adapter_nsrst_delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# See STM Document RM0038
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# Section 30.6.3 - corresponds to Cortex-M3 r2p0
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set _CPUTAPID 0x4ba00477
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} else {
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# SWD IDCODE (single drop, arm)
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set _CPUTAPID 0x2ba01477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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if { [info exists BSTAPID] } {
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# FIXME this never gets used to override defaults...
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set _BSTAPID $BSTAPID
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} else {
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# See STM Document RM0038 Section 30.6.1
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# (section 30.6.2 seems incorrect, at least in RM0038 DocID 15965 Rev 10)
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# Low and medium density
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set _BSTAPID1 0x06416041
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# Cat.3 device (medium+ density)
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set _BSTAPID2 0x06427041
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# Cat.4 device, STM32L15/6xxD or Cat.3 device, some STM32L15/6xxC-A models
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set _BSTAPID3 0x06436041
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# Cat.5 device (high density), STM32L15/6xxE
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set _BSTAPID4 0x06437041
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}
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if {[using_jtag]} {
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swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# flash size will be probed
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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proc stm32l_enable_HSI {} {
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# Enable HSI as clock source
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echo "STM32L: Enabling HSI"
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# Set HSION in RCC_CR
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mww 0x40023800 0x00000101
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# Set HSI as SYSCLK
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mww 0x40023808 0x00000001
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# Increase JTAG speed
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adapter_khz 2000
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}
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$_TARGETNAME configure -event reset-init {
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stm32l_enable_HSI
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}
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$_TARGETNAME configure -event reset-start {
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adapter_khz 300
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}
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