2f8ddc0835
Move the ti targets to a TI folder. Since the folder is ti, we can
drop the "ti" prefix from the files themselves.
Done via the following script:
mkdir target/ti
FILES=`ls target/ti*.cfg target/omap*.cfg target/am335x.cfg
target/amdm37x.cfg target/icepick.cfg target/stellaris.cfg
target/davinci.cfg`
for cname in $FILES
do
bname=`basename $cname`
nname=`echo $bname|sed -e "s/^ti-//g"|sed -e "s/ti_//g"`
npath="target/ti/$nname"
echo "$cname => $npath"
fref=`git grep $cname .|cut -d ':' -f1|sort -u`
sed -i -e "s&$cname&$npath&g" $fref
git mv $cname $npath
done
Change-Id: I9f94dc6bb01f73721d4ff96be92cb51de2cbf0e2
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9203
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
77 lines
2.4 KiB
INI
77 lines
2.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# TI OMAP3530
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# http://focus.ti.com/docs/prod/folders/print/omap3530.html
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# Other OMAP3 chips remove DSP and/or the OpenGL support
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME omap3530
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}
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# ICEpick-C ... used to route Cortex, DSP, and more not shown here
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source [find target/ti/icepick.cfg]
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# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
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jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
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# Subsidiary TAP: CoreSight Debug Access Port (DAP)
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x0b6d602f
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_DAP_TAPID -disable
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jtag configure $_CHIPNAME.cpu -event tap-enable \
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"icepick_c_tapenable $_CHIPNAME.jrc 3"
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# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
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if { [info exists JRC_TAPID] } {
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set _JRC_TAPID $JRC_TAPID
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} else {
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set _JRC_TAPID 0x0b7ae02f
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
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-expected-id $_JRC_TAPID
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# GDB target: Cortex-A8, using DAP
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set _TARGETNAME $_CHIPNAME.cpu
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
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# SRAM: 64K at 0x4020.0000; use the first 16K
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$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
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###################
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# the reset sequence is event-driven
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# and kind of finicky...
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# some TCK tycles are required to activate the DEBUG power domain
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jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
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# have the DAP "always" be active
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jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
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proc omap3_dbginit {target} {
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# General Cortex-A8 debug initialisation
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cortex_a dbginit
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# Enable DBGU signal for OMAP353x
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$target mww phys 0x5401d030 0x00002000
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}
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# be absolutely certain the JTAG clock will work with the worst-case
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# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
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# OK to speed up *after* PLL and clock tree setup.
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adapter speed 1000
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# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
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# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
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# would issue. RST_DPLL3 (4) is a cold reset.
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set PRM_RSTCTRL 0x48307250
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$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
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$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"
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