Evgeniy Didin
435e6101c6
With this commit we add tcl files which describes ARCv2 architecture features and configure files for ARCv2 EMSK board. Changes since v1: -Moved from http://openocd.zylin.com/#/c/5332/4 into separate commit. Changes: 22.01.2020: -Removed "actionpoints" handling code in tcl/cpu/arc/v2.tcl because this capability is not supported yet. Changes: 17.03.2020: -Update Licence headers -Cleanup indents -Removed "reset halt" in boards .tcl -Updated adapter frequency commands Changes: 15.03.2020: -Removed "init" in the of boards .tcl Change-Id: I51bf620abe7b8e046e1dccc861a7d963965d3a42 Signed-off-by: Evgeniy Didin <didin@synopsys.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5350 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
23 lines
614 B
INI
23 lines
614 B
INI
# Copyright (C) 2014-2016,2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Synopsys DesignWare ARC EM Starter Kit v2.x
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#
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# Configure JTAG cable
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# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
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source [find interface/ftdi/digilent-hs1.cfg]
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# 5MHz seems to work good with all cores that might happen in 2.x
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adapter speed 5000
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# ARCs support only JTAG.
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transport select jtag
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# Configure FPGA. This script supports both LX45 and LX150.
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source [find target/snps_em_sk_fpga.cfg]
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