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3483756cba5038335654bee437b5f17b7e6b88fd
openocd/src/target/riscv
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Tomas Vanek 3483756cba target/riscv: check nextdm address in abits range 
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1257
developed by Mark Zhuang <mark.zhuang@spacemit.com>

When abits not correctly configured, we hope to detect it
as soon as possible.

Change-Id: I0b7b170c39761fb531dda0747f88ace3f39ae03b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9141
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
2025-11-12 20:32:10 +00:00
..
batch.c
target: riscv: don't test 'debug_level' directly
2025-11-12 20:17:21 +00:00
batch.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
debug_defines.c
target: riscv: Drop new typedefs added by the updated riscv-debug-spec files
2025-11-12 20:16:13 +00:00
debug_defines.h
target: riscv: Drop new typedefs added by the updated riscv-debug-spec files
2025-11-12 20:16:13 +00:00
debug_reg_printer.c
target: riscv: Drop new typedefs added by the updated riscv-debug-spec files
2025-11-12 20:16:13 +00:00
debug_reg_printer.h
target: riscv: Drop new typedefs added by the updated riscv-debug-spec files
2025-11-12 20:16:13 +00:00
encoding.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
field_helpers.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
gdb_regs.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
Makefile.am
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
opcodes.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
program.c
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
program.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv_reg_impl.h
target: riscv: align switch and case statements
2025-11-12 20:16:51 +00:00
riscv_reg.c
target: riscv: align switch and case statements
2025-11-12 20:16:51 +00:00
riscv_reg.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv_semihosting.c
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv-011_reg.c
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv-011_reg.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv-011.c
target: riscv-011: don't change 'debug_level' during target polling
2025-11-12 20:18:36 +00:00
riscv-011.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv-013_reg.c
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv-013_reg.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv-013.c
target/riscv: check nextdm address in abits range
2025-11-12 20:32:10 +00:00
riscv-013.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv.c
target/riscv: fix checking of number of parameters
2025-11-12 20:30:12 +00:00
riscv.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
startup.tcl
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00