Tobias Diedrich
6b9d19d367
Supported SoCs: AR71xx, AR724x, AR91xx, AR93xx, QCA9558 Extended and revised version of my original patch submitted by Dmytro here: http://openocd.zylin.com/#/c/3390 This driver is using pure SPI mode, so the flash base address is not used except some flash commands (e.g. "flash program") need it to distinguish the banks. Example config with all 3 chip selects: flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2 Example usage: > flash probe flash0 Found flash device 'win w25q128fv' (ID 0x001840ef) flash 'ath79' found at 0x00000000 > flash probe flash1 No SPI flash found > flash probe flash2 No SPI flash found > flash banks > flash read_bank flash0 /tmp/test.bin 0x00000000 0x1000 reading 4096 bytes from flash @0x00000000 wrote 4096 bytes to file /tmp/test.bin from flash bank 0 at offset 0x00000000 in 28.688066s (0.139 KiB/s) Change-Id: I5feb697722c07e83a9c1b361a9db7b06bc699aa8 Signed-off-by: Tobias Diedrich <ranma+openocd@tdiedrich.de> Reviewed-on: http://openocd.zylin.com/3612 Tested-by: jenkins Reviewed-by: Dmytro <dioptimizer@hotmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
125 lines
5.1 KiB
C
125 lines
5.1 KiB
C
/***************************************************************************
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by David T.L. Wong *
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* *
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* Copyright (C) 2011 by Drasko DRASKOVIC *
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* drasko.draskovic@gmail.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_MIPS32_PRACC_H
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#define OPENOCD_TARGET_MIPS32_PRACC_H
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#include <target/mips32.h>
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#include <target/mips_ejtag.h>
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#define MIPS32_PRACC_FASTDATA_AREA 0xFF200000
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#define MIPS32_PRACC_FASTDATA_SIZE 16
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#define MIPS32_PRACC_BASE_ADDR 0xFF200000
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#define MIPS32_PRACC_TEXT 0xFF200200
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#define MIPS32_PRACC_PARAM_OUT 0xFF202000
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#define PRACC_UPPER_BASE_ADDR (MIPS32_PRACC_BASE_ADDR >> 16)
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#define PRACC_MAX_CODE (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_TEXT)
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#define PRACC_MAX_INSTRUCTIONS (PRACC_MAX_CODE / 4)
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#define PRACC_OUT_OFFSET (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_BASE_ADDR)
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#define MIPS32_FASTDATA_HANDLER_SIZE 0x80
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#define UPPER16(uint32_t) (uint32_t >> 16)
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#define LOWER16(uint32_t) (uint32_t & 0xFFFF)
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#define NEG16(v) (((~(v)) + 1) & 0xFFFF)
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#define SWAP16(v) ((LOWER16(v) << 16) | (UPPER16(v)))
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/*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF)*/
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#define PRACC_BLOCK 128 /* 1 Kbyte */
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typedef struct {
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uint32_t instr;
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uint32_t addr;
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} pa_list;
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struct pracc_queue_info {
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struct mips_ejtag *ejtag_info;
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unsigned isa;
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int retval;
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int code_count;
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int store_count;
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int max_code; /* max intstructions with currently allocated memory */
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pa_list *pracc_list; /* Code and store addresses at dmseg */
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};
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void pracc_queue_init(struct pracc_queue_info *ctx);
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void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr);
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void pracc_add_li32(struct pracc_queue_info *ctx, uint32_t reg_num, uint32_t data, bool optimize);
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void pracc_queue_free(struct pracc_queue_info *ctx);
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int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info,
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struct pracc_queue_info *ctx, uint32_t *buf, bool check_last);
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int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info,
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uint32_t addr, int size, int count, void *buf);
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int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info,
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uint32_t addr, int size, int count, const void *buf);
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int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source,
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int write_t, uint32_t addr, int count, uint32_t *buf);
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int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
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int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
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int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx,
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uint32_t *param_out, bool check_last);
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/**
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* \b mips32_cp0_read
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*
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* Simulates mfc0 ASM instruction (Move From C0),
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* i.e. implements copro C0 Register read.
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*
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* @param[in] ejtag_info
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* @param[in] val Storage to hold read value
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* @param[in] cp0_reg Number of copro C0 register we want to read
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* @param[in] cp0_sel Select for the given C0 register
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*
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* @return ERROR_OK on Sucess, ERROR_FAIL otherwise
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*/
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int mips32_cp0_read(struct mips_ejtag *ejtag_info,
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uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel);
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/**
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* \b mips32_cp0_write
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*
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* Simulates mtc0 ASM instruction (Move To C0),
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* i.e. implements copro C0 Register read.
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*
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* @param[in] ejtag_info
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* @param[in] val Value to be written
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* @param[in] cp0_reg Number of copro C0 register we want to write to
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* @param[in] cp0_sel Select for the given C0 register
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*
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* @return ERROR_OK on Sucess, ERROR_FAIL otherwise
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*/
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int mips32_cp0_write(struct mips_ejtag *ejtag_info,
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uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel);
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inline void pracc_swap16_array(struct mips_ejtag *ejtag_info, uint32_t *buf, int count)
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{
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if (ejtag_info->isa && ejtag_info->endianness)
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for (int i = 0; i != count; i++)
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buf[i] = SWAP16(buf[i]);
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}
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#endif /* OPENOCD_TARGET_MIPS32_PRACC_H */
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