04c6a6ee0e
Add configuration files for Espressif RISC-V based chips: - ESP32-C2, ESP32-C3, ESP32-C6, ESP32-H2 target configs - Board configs for builtin USB-JTAG and FTDI interfaces while adding the new config files: - Fix indentation in existing Espressif config files - Adapt esp_common.cfg with RISC-V support - Add explicit 'transport select jtag' to interface configs to avoid 'DEPRECATED: auto-selecting transport' warning Change-Id: I45fcbca2fe50888750e2e98a0a6773de86aad6d0 Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Reviewed-on: https://review.openocd.org/c/openocd/+/9195 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
125 lines
3.8 KiB
INI
125 lines
3.8 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Source the ESP common configuration file.
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source [find target/esp_common.cfg]
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# Target specific global variables
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set _CHIPNAME "esp32c2"
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set _CPUTAPID "0x0000cc25"
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set _ESP_ARCH "riscv"
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set _ONLYCPU 1
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set _ESP_SMP_TARGET 0
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set _ESP_SMP_BREAK 0
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set _ESP_EFUSE_MAC_ADDR_REG 0x60008840
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# Target specific functions should be implemented for each riscv chips.
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proc esp32c2_wdt_disable { } {
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# Halt event can occur during config phase (before "init" is done).
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# Ignore it since mww commands don't work at that time.
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if { [string compare [command mode] config] == 0 } {
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return
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}
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# Disable Timer Group 0 WDT
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mww 0x6001f064 0x50D83AA1
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mww 0x6001F048 0
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# Clear TG0 wdt interrupt state
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mww 0x6001F07C 0x2
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# Disable RTC WDT
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mww 0x6000809C 0x50D83AA1
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mww 0x60008084 0
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# Disable Super WDT
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mww 0x600080A4 0x8F1D312A
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mww 0x600080A0 0x84B00000
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# Clear RTC and Super wdt interrupt states
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mww 0x60008044 0x8008
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}
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proc esp32c2_soc_reset { } {
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global _RISCV_DMCONTROL
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# This procedure does "digital system reset", i.e. resets
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# all the peripherals except for the RTC block.
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# It is called from reset-assert-post target event callback,
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# after assert_reset procedure was called.
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# Since we need the hart to execute a write to RTC_CNTL_SW_SYS_RST,
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# temporarily take it out of reset. Save the dmcontrol state before
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# doing so.
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riscv dmi_write $_RISCV_DMCONTROL 0x80000001
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# Trigger the reset
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mww 0x60008000 0x9c00a000
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# Workaround for stuck in cpu start during calibration.
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# By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration
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mww 0x6001F068 0
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# Wait for the reset to happen
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sleep 10
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poll
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# Disable the watchdogs again
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esp32c2_wdt_disable
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# Here debugger reads allresumeack and allhalted bits as set (0x330a2)
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# We will clean allhalted state by resuming the core.
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riscv dmi_write $_RISCV_DMCONTROL 0x40000001
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# Put the hart back into reset state. Note that we need to keep haltreq set.
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riscv dmi_write $_RISCV_DMCONTROL 0x80000003
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}
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proc esp32c2_memprot_is_enabled { } {
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global _RISCV_ABS_CMD _RISCV_ABS_DATA0
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# PMPADDR 0-1 covers entire valid IRAM range and PMPADDR 2-3 covers entire DRAM region
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# pmpcfg0 holds the configuration for the PMP 0-3 address registers
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# read pmpcfg0 and extract into 8-bit variables.
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riscv dmi_write $_RISCV_ABS_CMD 0x2203a0
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set pmpcfg0 [riscv dmi_read $_RISCV_ABS_DATA0]
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set pmp0cfg [expr {($pmpcfg0 >> (8 * 0)) & 0xFF}]
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set pmp1cfg [expr {($pmpcfg0 >> (8 * 1)) & 0xFF}]
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set pmp2cfg [expr {($pmpcfg0 >> (8 * 2)) & 0xFF}]
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set pmp3cfg [expr {($pmpcfg0 >> (8 * 3)) & 0xFF}]
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# read PMPADDR 0-3
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riscv dmi_write $_RISCV_ABS_CMD 0x2203b0
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set pmpaddr0 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
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riscv dmi_write $_RISCV_ABS_CMD 0x2203b1
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set pmpaddr1 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
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riscv dmi_write $_RISCV_ABS_CMD 0x2203b2
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set pmpaddr2 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
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riscv dmi_write $_RISCV_ABS_CMD 0x2203b3
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set pmpaddr3 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
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set IRAM_LOW 0x40380000
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set IRAM_HIGH 0x403C0000
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set DRAM_LOW 0x3FCA0000
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set DRAM_HIGH 0x3FCE0000
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set PMP_RWX 0x07
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set PMP_RW 0x03
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# The lock bit remains unset during the execution of the 2nd stage bootloader.
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# Thus we do not perform a lock bit check for IRAM and DRAM regions.
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# Check OpenOCD can write and execute from IRAM.
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if {$pmpaddr0 >= $IRAM_LOW && $pmpaddr1 <= $IRAM_HIGH} {
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if {($pmp0cfg & $PMP_RWX) != 0 || ($pmp1cfg & $PMP_RWX) != $PMP_RWX} {
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return 1
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}
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}
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# Check OpenOCD can read/write entire DRAM region.
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if {$pmpaddr2 >= $DRAM_LOW && $pmpaddr3 <= $DRAM_HIGH} {
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if {($pmp2cfg & $PMP_RW) != 0 && ($pmp3cfg & $PMP_RW) != $PMP_RW} {
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return 1
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}
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}
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return 0
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}
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create_esp_target $_ESP_ARCH
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