ceaa47a2aa
This new code implement two FIFOs for handling TX and RX JTAG data transfers, its simply receives data and send it OUT to target chip in respect of JTAG protocol timing constraints. The IN FIFO receives data from target chip and send it back to openocd. Change-Id: I17c1231e7f4b0a6b510359fe147b609922e0809e Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8715 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
33 lines
882 B
VHDL
33 lines
882 B
VHDL
library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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entity clk_div is
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Port (
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clk_in : in std_logic;
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reset : in std_logic;
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clk_out : out std_logic
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);
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end clk_div;
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architecture behavioral of clk_div is
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-- Division factor N = 4, so we need a 2-bit counter (2^2 = 4)
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-- signal counter : unsigned(1 downto 0) := (others => '0');
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signal tmp : std_logic;
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begin
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process(clk_in, reset)
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begin
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if reset = '1' then
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-- counter <= (others => '0');
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tmp <= '0';
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elsif rising_edge(clk_in) then
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-- if counter = (2**2 - 1) then
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-- counter <= (others => '0');
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tmp <= NOT tmp; -- Toggle the output clock
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-- else
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-- counter <= counter + 1;
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-- end if;
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end if;
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end process;
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clk_out <= tmp;
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end behavioral; |