03b79387cc
The STM32H7R/H7Sx has a flash size up to 64 Kb Change-Id: I2e9d80758d1bc88defdd6bbd1787026373b39fa4 Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8890 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
99 lines
2.7 KiB
INI
99 lines
2.7 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# script for stm32h7rsx family
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#
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# stm32h7rs devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32h7rsx
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}
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# Issue an error when hla is used
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if { [using_hla] } {
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echo "Error : hla does not support STM32H7RS devices"
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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set _CPUTAPID 0x6ba00477
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} {
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set _CPUTAPID 0x6ba02477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0
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target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 1
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# test ram area
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$_CHIPNAME.cpu0 configure -work-area-phys 0x24000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.flash stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
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# Make sure that cpu0 is selected
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targets $_CHIPNAME.cpu0
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# Clock after reset is HSI at 64 MHz, no need of PLL
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adapter speed 4000
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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# use hardware reset
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#
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# The STM32H7RS does not support connect_assert_srst mode because the AXI is
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# unavailable while SRST is asserted, and that is used to access the DBGMCU
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# component at 0x5C001000 in the examine-end event handler.
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#
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reset_config srst_gates_jtag
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
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# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
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# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
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# makes the data access cacheable. This allows reading and writing data in the
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# CPU cache from the debugger, which is far more useful than going straight to
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# RAM when operating on typical variables, and is generally no worse when
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# operating on special memory locations.
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$_CHIPNAME.dap apcsw 0x08000000 0x08000000
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}
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$_CHIPNAME.cpu0 configure -event examine-end {
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0x5C001004 0x00000007 0
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# Enable clock for tracing
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# DBGMCU_CR |= TRACECLKEN
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mmw 0x5C001004 0x00100000 0
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}
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