22bad00b9b
The STM32U0xx devices support only SWD. Add swd transport in the target file. Remove swd transport from the associated board files. Change-Id: I2d31856951d15fcf2d1986ee5b1b31464e68db1c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/9427 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins Reviewed-by: Ahmed Haoues <ahmed.haoues@st.com>
57 lines
1.4 KiB
INI
57 lines
1.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# Configuration file for STM32U0x series.
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#
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# STM32U0 devices support only SWD transport.
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#
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transport select swd
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32u0x
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}
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# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x1000
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x6ba02477
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}
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swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x1FFF6800 0 0 0 $_TARGETNAME
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adapter speed 2000
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if {![using_hla]} {
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# Use SYSRESETREQ to perform a soft reset if SRST is not fitted.
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event examine-end {
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# Enable debug during low power modes (uses more power).
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
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mmw 0x40015804 0x00000006 0
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# Stop watchdog counters when core is halted.
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# DBGMCU_APB1_FZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0x40015808 0x00001800 0
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}
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