Embedded flash also has a user signature area. This is a 512 bytes large page whose data are not erased by asserting ERASE pin or by software ERASE command. It may be used to store configuration, keys, trimming values etc. This commit adds option to access this area from OpenOCD. Change-Id: If870aa85938b9cccd94f958dd1f3d93dbdf779f0 Signed-off-by: Michal Lenc <michallenc@seznam.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/8302 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
64 lines
1.9 KiB
INI
64 lines
1.9 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
|
|
|
|
# ATMEL SAMV, SAMS, and SAME chips are Cortex-M7 parts
|
|
# The chips are very similar; the SAMV series just has
|
|
# more peripherals and seems like the "flagship" of the
|
|
# family. This script will work for all of them.
|
|
|
|
source [find target/swj-dp.tcl]
|
|
|
|
if { [info exists CHIPNAME] } {
|
|
set _CHIPNAME $CHIPNAME
|
|
} else {
|
|
set _CHIPNAME samv
|
|
}
|
|
|
|
if { [info exists ENDIAN] } {
|
|
set _ENDIAN $ENDIAN
|
|
} else {
|
|
set _ENDIAN little
|
|
}
|
|
|
|
# Work-area is a space in RAM used for flash programming
|
|
# By default use 16kB
|
|
if { [info exists WORKAREASIZE] } {
|
|
set _WORKAREASIZE $WORKAREASIZE
|
|
} else {
|
|
set _WORKAREASIZE 0x4000
|
|
}
|
|
|
|
if { [info exists CPUTAPID] } {
|
|
set _CPUTAPID $CPUTAPID
|
|
} else {
|
|
set _CPUTAPID 0x0bd11477
|
|
}
|
|
|
|
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
|
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
|
|
|
|
set _TARGETNAME $_CHIPNAME.cpu
|
|
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
|
|
|
|
$_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
|
|
|
adapter speed 1800
|
|
|
|
if {![using_hla]} {
|
|
# if srst is not fitted use SYSRESETREQ to
|
|
# perform a soft reset
|
|
cortex_m reset_config sysresetreq
|
|
|
|
# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
|
|
# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
|
|
# makes the data access cacheable. This allows reading and writing data in the
|
|
# CPU cache from the debugger, which is far more useful than going straight to
|
|
# RAM when operating on typical variables, and is generally no worse when
|
|
# operating on special memory locations.
|
|
$_CHIPNAME.dap apcsw 0x08000000 0x08000000
|
|
}
|
|
|
|
set _FLASHNAME $_CHIPNAME.flash
|
|
set _SIGNATURENAME $_CHIPNAME.usersignature
|
|
flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
|
|
flash bank $_SIGNATURENAME atsamv 0x100000000 0 0 0 $_TARGETNAME
|