a51ab8ddf6
This supports both 0.11 and 0.13 versions of the debug spec. Support for `-rtos riscv` will come in a separate commit since it was easy to separate out, and is likely to be more controversial. Flash support for the SiFive boards will also come in a later commit. Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190 Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/4578 Tested-by: jenkins Reviewed-by: Liviu Ionescu <ilg@livius.net> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
39 lines
1015 B
C
39 lines
1015 B
C
#ifndef TARGET__RISCV__ASM_H
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#define TARGET__RISCV__ASM_H
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#include "riscv.h"
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/*** Version-independent functions that we don't want in the main address space. ***/
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static uint32_t load(const struct target *target, unsigned int rd,
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unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t load(const struct target *target, unsigned int rd,
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unsigned int base, uint16_t offset)
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{
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switch (riscv_xlen(target)) {
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case 32:
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return lw(rd, base, offset);
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case 64:
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return ld(rd, base, offset);
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}
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assert(0);
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return 0; /* Silence -Werror=return-type */
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}
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static uint32_t store(const struct target *target, unsigned int src,
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unsigned int base, uint16_t offset) __attribute__ ((unused));
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static uint32_t store(const struct target *target, unsigned int src,
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unsigned int base, uint16_t offset)
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{
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switch (riscv_xlen(target)) {
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case 32:
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return sw(src, base, offset);
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case 64:
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return sd(src, base, offset);
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}
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assert(0);
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return 0; /* Silence -Werror=return-type */
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}
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#endif
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