7b4428df97
- remove endianness options; these chips hard-wire "little"
- $_TARGETNAME updates:
* don't pass $_TARGETNAME where a TAP label is required
* flash config uses $_TARGETNAME (it might not be target #0)
* simplify one $_TARGETNAME construction
- update work area setup:
* remove VM spec; these chips have no VM!
* fix some wrong sizes (0x4000 == 16K, not 4K)
* simplify: take defaults
- comment fixups
git-svn-id: svn://svn.berlios.de/openocd/trunk@2589 b42882b7-edfa-0310-969c-e2dbd0fdcd60
38 lines
954 B
INI
38 lines
954 B
INI
# TI/Luminary Stellaris lm3s6965
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME lm3s6965
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x3ba00477
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}
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# jtag speed
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jtag_khz 500
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jtag_nsrst_delay 100
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jtag_ntrst_delay 100
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#LM3S6965 Evaluation Board has only srst
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reset_config srst_only
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#jtag scan chain
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
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# the luminary variant causes a software reset rather than asserting SRST
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# this stops the debug registers from being cleared
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# this will be fixed in later revisions of silicon
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3s
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# 8k working area at base of ram, not backed up
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
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#flash configuration
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flash bank stellaris 0 0 0 0 $_TARGETNAME
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