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openocd/src/target/riscv
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Evgeniy Naydanov 4e78563a00 target/riscv: fix progbuf memory writes in case last write is busy 
Restarting the program buffer memory write pipeline when the write of
the last element resulted in the busy response triggers an extra memory
wrtite, that is cought by an assertion:
```
src/target/riscv/riscv-013.c:5048: write_memory_progbuf_inner: Assertion
`next_addr_on_target - args.address <= (target_addr_t)args.size *
args.count' failed.
```

Change-Id: I0f27145cad24686cf539aebfea7f6578b7cd78ab
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9233
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-11-12 20:53:02 +00:00
..
batch.c
target: riscv: don't test 'debug_level' directly
2025-11-12 20:17:21 +00:00
batch.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
debug_defines.c
target: riscv: Drop new typedefs added by the updated riscv-debug-spec files
2025-11-12 20:16:13 +00:00
debug_defines.h
target: riscv: Drop new typedefs added by the updated riscv-debug-spec files
2025-11-12 20:16:13 +00:00
debug_reg_printer.c
target: riscv: Drop new typedefs added by the updated riscv-debug-spec files
2025-11-12 20:16:13 +00:00
debug_reg_printer.h
target: riscv: Drop new typedefs added by the updated riscv-debug-spec files
2025-11-12 20:16:13 +00:00
encoding.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
field_helpers.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
gdb_regs.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
Makefile.am
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
opcodes.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
program.c
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
program.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv_reg_impl.h
target: riscv: align switch and case statements
2025-11-12 20:16:51 +00:00
riscv_reg.c
target: riscv: align switch and case statements
2025-11-12 20:16:51 +00:00
riscv_reg.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv_semihosting.c
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv-011_reg.c
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv-011_reg.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv-011.c
target: riscv-011: don't change 'debug_level' during target polling
2025-11-12 20:18:36 +00:00
riscv-011.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv-013_reg.c
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv-013_reg.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv-013.c
target/riscv: fix progbuf memory writes in case last write is busy
2025-11-12 20:53:02 +00:00
riscv-013.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
riscv.c
target/riscv: fix SV57 translation for kernel address space
2025-11-12 20:52:25 +00:00
riscv.h
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00
startup.tcl
target: riscv: Sync with the RISC-V fork
2025-11-12 20:14:47 +00:00