8704e53665
ARMv7 architecture allows up to 7 cache levels that are architecturally visible, as opposed to "system caches", which are outside of the domain defined by ARMv7 and require separate management. This patch enables detection and identification of caches at all levels. It also implements a new "flush-all" function that cleans & invalidates all cache levels to the "Point of Coherence". Change-Id: Ib77115d6044d39845907941c6f031e208f6e0aa5 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3024 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
561 lines
14 KiB
C
561 lines
14 KiB
C
/***************************************************************************
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* Copyright (C) 2015 by Oleksij Rempel *
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* linux@rempel-privat.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "jtag/interface.h"
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#include "arm.h"
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#include "armv7a.h"
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#include "armv7a_cache.h"
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#include <helper/time_support.h>
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#include "arm_opcodes.h"
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static int armv7a_l1_d_cache_sanity_check(struct target *target)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("%s: target not halted", __func__);
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return ERROR_TARGET_NOT_HALTED;
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}
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/* check that cache data is on at target halt */
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if (!armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) {
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LOG_DEBUG("l1 data cache is not enabled");
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return ERROR_TARGET_INVALID;
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}
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return ERROR_OK;
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}
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static int armv7a_l1_i_cache_sanity_check(struct target *target)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("%s: target not halted", __func__);
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return ERROR_TARGET_NOT_HALTED;
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}
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/* check that cache data is on at target halt */
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if (!armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) {
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LOG_DEBUG("l1 data cache is not enabled");
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return ERROR_TARGET_INVALID;
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}
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return ERROR_OK;
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}
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static int armv7a_l1_d_cache_flush_level(struct arm_dpm *dpm, struct armv7a_cachesize *size, int cl)
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{
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int retval = ERROR_OK;
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int32_t c_way, c_index = size->index;
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LOG_DEBUG("cl %" PRId32, cl);
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do {
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c_way = size->way;
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do {
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uint32_t value = (c_index << size->index_shift)
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| (c_way << size->way_shift) | (cl << 1);
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/*
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* DCCISW - Clean and invalidate data cache
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* line by Set/Way.
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*/
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
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value);
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if (retval != ERROR_OK)
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goto done;
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c_way -= 1;
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} while (c_way >= 0);
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c_index -= 1;
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} while (c_index >= 0);
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done:
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return retval;
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}
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static int armv7a_l1_d_cache_clean_inval_all(struct target *target)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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int cl;
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int retval;
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retval = armv7a_l1_d_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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for (cl = 0; cl < cache->loc; cl++) {
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/* skip i-only caches */
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if (cache->arch[cl].ctype < CACHE_LEVEL_HAS_D_CACHE)
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continue;
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armv7a_l1_d_cache_flush_level(dpm, &cache->arch[cl].d_u_size, cl);
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}
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retval = dpm->finish(dpm);
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return retval;
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done:
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LOG_ERROR("clean invalidate failed");
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dpm->finish(dpm);
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return retval;
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}
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int armv7a_cache_auto_flush_all_data(struct target *target)
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{
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int retval = ERROR_FAIL;
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struct armv7a_common *armv7a = target_to_armv7a(target);
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if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled)
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return ERROR_OK;
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if (target->smp) {
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struct target_list *head;
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struct target *curr;
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head = target->head;
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while (head != (struct target_list *)NULL) {
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curr = head->target;
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if (curr->state == TARGET_HALTED)
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retval = armv7a_l1_d_cache_clean_inval_all(curr);
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head = head->next;
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}
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} else
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retval = armv7a_l1_d_cache_clean_inval_all(target);
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/* do outer cache flushing after inner caches have been flushed */
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retval = arm7a_l2x_flush_all_data(target);
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return retval;
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}
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static int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt,
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uint32_t size)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
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uint32_t i, linelen = armv7a_cache->dminline;
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int retval;
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retval = armv7a_l1_d_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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for (i = 0; i < size; i += linelen) {
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uint32_t offs = virt + i;
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/* DCIMVAC - Clean and invalidate data cache line by VA to PoC. */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 6, 1), offs);
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if (retval != ERROR_OK)
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goto done;
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}
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return retval;
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done:
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LOG_ERROR("d-cache invalidate failed");
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dpm->finish(dpm);
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return retval;
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}
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int armv7a_l1_d_cache_clean_virt(struct target *target, uint32_t virt,
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unsigned int size)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
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uint32_t i, linelen = armv7a_cache->dminline;
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int retval;
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retval = armv7a_l1_d_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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for (i = 0; i < size; i += linelen) {
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uint32_t offs = virt + i;
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/* FIXME: do we need DCCVAC or DCCVAU */
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/* FIXME: in both cases it is not enough for i-cache */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 10, 1), offs);
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if (retval != ERROR_OK)
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goto done;
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}
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return retval;
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done:
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LOG_ERROR("d-cache invalidate failed");
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dpm->finish(dpm);
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return retval;
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}
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int armv7a_l1_i_cache_inval_all(struct target *target)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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int retval;
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retval = armv7a_l1_i_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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if (target->smp) {
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/* ICIALLUIS */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 1, 0), 0);
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} else {
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/* ICIALLU */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 5, 0), 0);
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}
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if (retval != ERROR_OK)
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goto done;
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dpm->finish(dpm);
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return retval;
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done:
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LOG_ERROR("i-cache invalidate failed");
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dpm->finish(dpm);
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return retval;
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}
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int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt,
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uint32_t size)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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struct armv7a_cache_common *armv7a_cache =
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&armv7a->armv7a_mmu.armv7a_cache;
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uint32_t linelen = armv7a_cache->iminline;
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uint32_t va_line, va_end;
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int retval;
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retval = armv7a_l1_i_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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va_line = virt & (-linelen);
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va_end = virt + size;
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while (va_line < va_end) {
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/* ICIMVAU - Invalidate instruction cache by VA to PoU. */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 5, 1), va_line);
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if (retval != ERROR_OK)
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goto done;
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/* BPIMVA */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 5, 7), va_line);
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if (retval != ERROR_OK)
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goto done;
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va_line += linelen;
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}
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return retval;
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done:
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LOG_ERROR("i-cache invalidate failed");
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dpm->finish(dpm);
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return retval;
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}
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/*
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* We assume that target core was chosen correctly. It means if same data
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* was handled by two cores, other core will loose the changes. Since it
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* is impossible to know (FIXME) which core has correct data, keep in mind
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* that some kind of data lost or korruption is possible.
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* Possible scenario:
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* - core1 loaded and changed data on 0x12345678
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* - we halted target and modified same data on core0
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* - data on core1 will be lost.
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*/
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int armv7a_cache_auto_flush_on_write(struct target *target, uint32_t virt,
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uint32_t size)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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int retval = ERROR_OK;
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if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled)
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return ERROR_OK;
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armv7a_l1_d_cache_clean_virt(target, virt, size);
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armv7a_l2x_cache_flush_virt(target, virt, size);
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if (target->smp) {
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struct target_list *head;
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struct target *curr;
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head = target->head;
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while (head != (struct target_list *)NULL) {
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curr = head->target;
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if (curr->state == TARGET_HALTED) {
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retval = armv7a_l1_i_cache_inval_all(curr);
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if (retval != ERROR_OK)
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return retval;
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retval = armv7a_l1_d_cache_inval_virt(target,
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virt, size);
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if (retval != ERROR_OK)
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return retval;
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}
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head = head->next;
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}
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} else {
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retval = armv7a_l1_i_cache_inval_all(target);
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if (retval != ERROR_OK)
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return retval;
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retval = armv7a_l1_d_cache_inval_virt(target, virt, size);
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if (retval != ERROR_OK)
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return retval;
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}
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return retval;
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}
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COMMAND_HANDLER(arm7a_l1_cache_info_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct armv7a_common *armv7a = target_to_armv7a(target);
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return armv7a_handle_cache_info_command(CMD_CTX,
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&armv7a->armv7a_mmu.armv7a_cache);
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}
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COMMAND_HANDLER(armv7a_l1_d_cache_clean_inval_all_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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armv7a_l1_d_cache_clean_inval_all(target);
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return 0;
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}
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COMMAND_HANDLER(arm7a_l1_d_cache_inval_virt_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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uint32_t virt, size;
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if (CMD_ARGC == 0 || CMD_ARGC > 2)
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return ERROR_COMMAND_SYNTAX_ERROR;
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if (CMD_ARGC == 2)
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
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else
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size = 1;
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
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return armv7a_l1_d_cache_inval_virt(target, virt, size);
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}
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COMMAND_HANDLER(arm7a_l1_d_cache_clean_virt_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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uint32_t virt, size;
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if (CMD_ARGC == 0 || CMD_ARGC > 2)
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return ERROR_COMMAND_SYNTAX_ERROR;
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if (CMD_ARGC == 2)
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
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else
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size = 1;
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
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return armv7a_l1_d_cache_clean_virt(target, virt, size);
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}
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COMMAND_HANDLER(armv7a_i_cache_clean_inval_all_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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armv7a_l1_i_cache_inval_all(target);
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return 0;
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}
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COMMAND_HANDLER(arm7a_l1_i_cache_inval_virt_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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uint32_t virt, size;
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if (CMD_ARGC == 0 || CMD_ARGC > 2)
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return ERROR_COMMAND_SYNTAX_ERROR;
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if (CMD_ARGC == 2)
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
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else
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size = 1;
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
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return armv7a_l1_i_cache_inval_virt(target, virt, size);
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}
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COMMAND_HANDLER(arm7a_cache_disable_auto_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct armv7a_common *armv7a = target_to_armv7a(target);
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if (CMD_ARGC == 0) {
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command_print(CMD_CTX, "auto cache is %s",
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armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled ? "enabled" : "disabled");
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return ERROR_OK;
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}
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if (CMD_ARGC == 1) {
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uint32_t set;
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COMMAND_PARSE_ENABLE(CMD_ARGV[0], set);
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armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled = !!set;
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return ERROR_OK;
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}
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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static const struct command_registration arm7a_l1_d_cache_commands[] = {
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{
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.name = "flush_all",
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.handler = armv7a_l1_d_cache_clean_inval_all_cmd,
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.mode = COMMAND_ANY,
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.help = "flush (clean and invalidate) complete l1 d-cache",
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.usage = "",
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},
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{
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.name = "inval",
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.handler = arm7a_l1_d_cache_inval_virt_cmd,
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.mode = COMMAND_ANY,
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.help = "invalidate l1 d-cache by virtual address offset and range size",
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.usage = "<virt_addr> [size]",
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},
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{
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.name = "clean",
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.handler = arm7a_l1_d_cache_clean_virt_cmd,
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.mode = COMMAND_ANY,
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.help = "clean l1 d-cache by virtual address address offset and range size",
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.usage = "<virt_addr> [size]",
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},
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COMMAND_REGISTRATION_DONE
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};
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static const struct command_registration arm7a_l1_i_cache_commands[] = {
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{
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.name = "inval_all",
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.handler = armv7a_i_cache_clean_inval_all_cmd,
|
|
.mode = COMMAND_ANY,
|
|
.help = "invalidate complete l1 i-cache",
|
|
.usage = "",
|
|
},
|
|
{
|
|
.name = "inval",
|
|
.handler = arm7a_l1_i_cache_inval_virt_cmd,
|
|
.mode = COMMAND_ANY,
|
|
.help = "invalidate l1 i-cache by virtual address offset and range size",
|
|
.usage = "<virt_addr> [size]",
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
const struct command_registration arm7a_l1_di_cache_group_handlers[] = {
|
|
{
|
|
.name = "info",
|
|
.handler = arm7a_l1_cache_info_cmd,
|
|
.mode = COMMAND_ANY,
|
|
.help = "print cache realted information",
|
|
.usage = "",
|
|
},
|
|
{
|
|
.name = "d",
|
|
.mode = COMMAND_ANY,
|
|
.help = "l1 d-cache command group",
|
|
.usage = "",
|
|
.chain = arm7a_l1_d_cache_commands,
|
|
},
|
|
{
|
|
.name = "i",
|
|
.mode = COMMAND_ANY,
|
|
.help = "l1 i-cache command group",
|
|
.usage = "",
|
|
.chain = arm7a_l1_i_cache_commands,
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
const struct command_registration arm7a_cache_group_handlers[] = {
|
|
{
|
|
.name = "auto",
|
|
.handler = arm7a_cache_disable_auto_cmd,
|
|
.mode = COMMAND_ANY,
|
|
.help = "disable or enable automatic cache handling.",
|
|
.usage = "(1|0)",
|
|
},
|
|
{
|
|
.name = "l1",
|
|
.mode = COMMAND_ANY,
|
|
.help = "l1 cache command group",
|
|
.usage = "",
|
|
.chain = arm7a_l1_di_cache_group_handlers,
|
|
},
|
|
{
|
|
.chain = arm7a_l2x_cache_command_handler,
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
const struct command_registration arm7a_cache_command_handlers[] = {
|
|
{
|
|
.name = "cache",
|
|
.mode = COMMAND_ANY,
|
|
.help = "cache command group",
|
|
.usage = "",
|
|
.chain = arm7a_cache_group_handlers,
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|