The CPLD on the xds100v2 expects to see a rising edge on PWR_RST to
enable the outputs. This patch creates that transition correctly by
fixing the direction register for PWR_RST.
THe CPLD will also loop back the data if the LOOPBACK signal is
asserted. Set this signal to an output and keep it clear.
This was tested with a TI DM3730 Beagleboard xM.
Change-Id: I4ea216bef6ae5c40e935741af5c69dc844d5d494
Signed-off-by: Kyle Manna <kyle.manna@fuel7.com>
Reviewed-on: http://openocd.zylin.com/189
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
87552bc1d3