ceaa47a2aa
This new code implement two FIFOs for handling TX and RX JTAG data transfers, its simply receives data and send it OUT to target chip in respect of JTAG protocol timing constraints. The IN FIFO receives data from target chip and send it back to openocd. Change-Id: I17c1231e7f4b0a6b510359fe147b609922e0809e Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8715 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
75 lines
2.3 KiB
Plaintext
75 lines
2.3 KiB
Plaintext
## SPDX-License-Identifier: BSD-3-Clause
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##--------------------------------------------------------------------------
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## Project Context: nanoXplore USB to JTAG/I2C Adapter Board, Spartan6
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## Design Name: ANGIE USB to JTAG/I2C Adapter FPGA source code
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## Module Name: angie_bitstream.ucf
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## Target Device: XC6SLX9-2 TQ144
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## Tool versions: ISE Webpack 13.2 -> 14.2
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## Author: Ahmed BOUDJELIDA nanoXplore SAS
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##--------------------------------------------------------------------------
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# WARNING: PullUps on JTAG inputs should be enabled after configuration
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# (bitgen option) since the pins are not connected.
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CONFIG VCCAUX = "3.3";
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# Timing
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# net IH24 period = 40; # Constrain at 25MHz
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# net IH40 period = 25; # Constrain at 40MHz
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# DCMs placement on Spartan6
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# INST S6MOD_CKMUL.H48_DCM LOC = DCM0;
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# Clock 48MHz
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net IFCLK_I LOC = 'P123' ;
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net GD_IO<0> LOC = 'P48' ;
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net GD_IO<1> LOC = 'P43' ;
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net GD_IO<2> LOC = 'P44' ;
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net GD_IO<3> LOC = 'P45' ;
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net GD_IO<4> LOC = 'P46' ;
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net GD_IO<5> LOC = 'P61' ;
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net GD_IO<6> LOC = 'P62' ;
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net GD_IO<7> LOC = 'P65' ;
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net PA2_I LOC = 'P47' ;
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#net PA3_I LOC = 'P64' ;
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net JPW_I LOC = 'P14' ;
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net GCTL0_I LOC = 'P70' ;
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#net GCTL1_I LOC = 'P55' ;
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#net GCTL2_I LOC = 'P67' ;
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net GRDY1_I LOC = 'P118' ;
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#net SDA_IO LOC = 'P50' ;
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net SDA_IO LOC = 'P64' ; #PA3
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#net SCL_I LOC = 'P51' ;
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net SCL_I LOC = 'P39' ; #PA4 switch
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net SDA_DIR_I LOC = 'P66' ; #PA0 switch
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#net SCL_DIR_I LOC = 'P57' ;
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net SO_SDA_OUT_O LOC = 'P140' ;
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net SO_SDA_IN_I LOC = 'P1' ;
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net SO_SCL_O LOC = 'P137' ;
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net SO_TRST_O LOC = 'P32' ;
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net SO_TMS_O LOC = 'P27' ;
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net SO_TCK_O LOC = 'P30' ;
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net SO_TDI_O LOC = 'P26' ;
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net SO_SRST_O LOC = 'P12' ;
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net SI_TDO_I LOC = 'P16' ;
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net ST_0_O LOC = 'P29' ;
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net ST_1_O LOC = 'P21' ;
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net ST_2_O LOC = 'P11' ;
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net ST_3_O LOC = 'P7' ;
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net ST_4_O LOC = 'P134' ;
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net ST_5_O LOC = 'P139' ;
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net FTP_O<0> LOC = 'P121' ;
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net FTP_O<1> LOC = 'P120' ;
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net FTP_O<2> LOC = 'P119' ;
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net FTP_O<3> LOC = 'P116' ;
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net FTP_O<4> LOC = 'P111' ;
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net FTP_O<5> LOC = 'P112' ;
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net FTP_O<6> LOC = 'P115' ;
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net FTP_O<7> LOC = 'P114' ;
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