d3f0549f08
Wrote a default flash erase check fn which uses CFI's target algorithm w/fallback to memory reads. - "flash info" no longer prints erase status as it is stale. - "flash erase_check" now prints erase status. erase check can take a *long* time. Work in progress - arm7/9 with seperate srst & trst now supports reset init/halt after a power outage. arm7/9 no longer makes any assumptions about state of target when reset is asserted. - fixes for srst & trst capable arm7/9 with reset init/halt - prepare_reset_halt retired. This code needs to be inside assert_reset anyway - haven't been able to get stm32 write algorithm to work. Fallback flash write does work. Haven't found a version of openocd trunk where this works. - added target_free_all_working_areas_restore() which can let be of restoring backups. This is needed when asserting reset as the target must be assumed to be an unknown state. Added some comments to working areas API - str9 reset script fixes - some guidelines - fixed dangling callbacks upon reset timeout git-svn-id: svn://svn.berlios.de/openocd/trunk@536 b42882b7-edfa-0310-969c-e2dbd0fdcd60
23 lines
885 B
Plaintext
23 lines
885 B
Plaintext
mww 0xFFFFFD44, 0x00008000 #Disable watchdog
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mww 0xFFFFFC20, 0x00000601 #Enable Main oscillator
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sleep 20
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mww 0xFFFFFC30, 0x00000001 #Switch master clock to CPU clock, write 1 to PMC_MCKR
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sleep 20
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# -- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,
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# when the bank 0 is the boot bank, then enable the Bank 1. */
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mww 0x54000000, 0x4 #BOOT BANK Size = (2^4) * 32 = 512KB
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mww 0x54000004, 0x2 #NON BOOT BANK Size = (2^2) * 8 = 32KB
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mww 0x5400000C, 0x0 #BOOT BANK Address = 0x0
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mww 0x54000010, 0x20000 #NON BOOT BANK Address = 0x80000
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mww 0x54000018, 0x18 #Enable CS on both banks
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# -- Enable 96K RAM */
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mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled
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arm966e cp15 15, 0x60000 #Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register
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str9x flash_config 0 4 2 0 0x80000
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flash protect 0 0 7 off
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